Preliminary W928C73
Publication Release Date: June 2000
- 9 - Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME
BIT
BIT NAME
R/W
1
0
INITIAL
FUNCTION
B2
IT1 R/W
High level
Low level
0
Interrupt 1 level selection. Set by software
to specify high (>0.8V) / low (<0.8V) level
external INT 1 triggered.
B1
IE0 R/W
INT
No INT
0
Interrupt 0 edge detect: Set by hardware
when an edge/level is detected on INT0.
This bit is cleared by hardware when the
service routine is vectored to only if the
interrupt was edge triggered. Otherwise it
follows the pin.
B0
IT0 R/W
Falling
edge
Low level
0
Interrupt 0 type selection. Set/cleared by
software to specify falling edge/ low level
triggered external inputs
B7
T1_GATE R/W
0
B6
T1_T R/W
Timer
0
B5
T1_M1 R/W
0
B4
T1_M0 R/W
0
B3
T0_GATE R/W
0
B2
T0_T R/W
Timer
0
B1
T0_M1 R/W
0
89H/TMOD
B0
T0_M0 R/W
0
Timer 1 & timer 0 control:
Tx_GATE (gating control):
When this bit is set, Timer/counter x will be
enabled if both INTx pin is high and TRx
control bit is set.
When this bit is cleared, Timerx is enabled
whenever TRx control bit is set.
Tx_C/T (timer or counter select):
When cleared, the timer is incremented by
internal clocks.
When set, the timer counts high-to-low
edges of the Tx pin.
M1 M0 Mode
0 0 8-bits with 5-bit pre-scalar.
0 1 16-bits, no pre-scalar.
1 0 8-bits with auto-reload from THx
1 1 (Timer 0) TL0 is an 8-bit
timer/counter controlled by the standard
Timer 0 control bits. TH0 is an 8-bit timer
only controlled by Timer 1 control bits.
(Timer 1) Timer/counter is stopped.
8AH/TL0
B7~0
TL0 R/W
00000000 Low byte of timer 0
8BH/TL1
B7~0
TL1 R/W
00000000 Low byte of timer 1
8CH/TH0
B7~0
TH0 R/W
00000000 High byte of timer 0
8DH/TH1
B7~0
TH1 R/W
00000000 High byte of timer 1
B7
WD1 R/W
0
B6
WD0 R/W
0
WD1 WD0 (watchdog timeout period)
0 0 Fs/2
14
+512 clock
0 1 Fs/2
16
+512 clock
1 0 Fs/2
18
+512 clock
1 1 Fs/2
21
+512 clock
B5
RTC1 R/W
0
8EH/CKCON
B4
RTC0 R/W
0
RTC1 RTC0 (RTC timeout period)
0 0 32 Hz for RTLCD = 74
0 1 8 Hz
1 0 2 Hz
1 1 1 Hz
