Preliminary W928C73
- 16 -
Data Pointers
The original 8031 had only one 16-bit Data Pointer (DPL, DPH). In the W928C73, there is an
additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which
were unused in the original 8031. In addition there is an additional instruction, DEC DPTR (op-code
A5H), which helps in improving programming flexibility for the user.
MOVX Instruction
The W928C73, like the standard 8031, uses the MOVX instruction to access the external Data
Memory. The external data memory includes
384
bytes on-chip data RAM.
The MOVX instruction is of two types, the MOVX @Ri and MOVX @DPTR. In the MOVX @Ri, the
address of the external data comes from two sources. The lower 8-bits of the address are stored in the
Ri register of the selected working register bank. The upper 8-bits of the address are store in the HB
register (B2h of SFR). In the MOVX @DPTR type, the full 16-bit address is supplied by the Data
Pointer.
Since the W928C73 has two Data Pointers, DPTR and DPTR1, the user has to select between the
two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR,
which exists at location 86h. Rest bits in this SFR have no effect, and are set to 0. When DPS is 0,
then DPTR is selected, and when set to 1, DPTR1 is selected. The user can switch between DPTR
and DPTR1 by toggling the DPS bit. The quickest way to do this is by the INC instruction. The HB
register and dual Data Pointers will provide enough flexibility for performing block move operations.
SYSTEM CLOCK
The W928C73 provides one oscillation circuit, OSC2 - L_clock (76.8 KHz), for the whole system.
During the power on reset, the L_clock is activated. The RTC Timer, WDT timer, buzzer output and
LCD frequency clock sources directly come from L_clock. The CPU, timer0, timer1 and interrupt
operation are based on the machine cycle. The machine cycle consists of four oscillator clock
sequence (4 states).
ELC is the control bit to activate the L_clock. The OVFL is the clock stable flag for the L_clock. The
power on state of system is ELC = 1. For proper operation, the L_clock is suggested to turn on all the
time. The clock architecture of the system is shown below.
L_Clock
/PD
/IDL
CPU
WDT,RTC,
LCD, BUZ
Timer/Counter 0, 1
Interrupt
ELC
OSC2
/4
