Preliminary W928C73
Publication Release Date: June 2000
- 31 - Revision A1
Flash Programming SFR Configuration
SFR NAME NAME
I/O
DESCRIPTION
P0.0
DATA
I/O Bi-direction data line
P0.2
ADDR
O
Output clock for start address shift-out
P3.4
CTRL
O
Enable signal for program and erase operations when MODE = 0 (P3.6)
Input clock for mode counter when MODE = 1 (P3.6)
P3.5
CLK
O
Output clock for data write-out and read-in
P3.6
MODE
O
Mode select control pin
•
Fast frame-write operation: Frame (32 bits) program cycle time: 400
µ
S (typical)
•
Fast whole-chip-erase duration: 50 mS (max.)
•
Read data access time: 500 nS (max.)
•
Program/erase cycles: 3000 (typical)
•
Data retention: 10 years (typical)
Notes:
1. program mode, the DATA should be latched in the CLK falling edge.
2. read mode, the DATA should be latched in before CLK low.
3. when in the read mode, must let P0IO.0 and P0.0 (DATA) set 1 ( input mode).
4. set GF1(general flag) to “1” will enable 1K flash.
DC CHARACTERISTICS
(V
DD
= 3V, V
SS
= 0V, T
A
= 25
°
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Operating Voltage
V
DD
-
2.4
3.6
V
Flash ROM Operating
Voltage
V
FLASH
-
2.5
3.6
V
Normal Mode Current
I
NORMAL
No load, decoder and CPU
operating at 76.8K Hz
100
µ
A
Idle Mode Current
I
IDLE
No load, main clock,
decoder on, CPU off
-
25
60
µ
A
Stop Mode Current
I
STOP
No load, OSC stop
1
µ
A
Flash ROM Operating
Current
I
OP
In read mode
DATA open
-
5
mA
High
V
IH
2.0
V
DD
V
Input Voltage
Low
V
IL
All input pins
-0.3
-
0.8
V
Sink
I
OL
V
OL
= 0.3V
0.6/0.1
mA
Output Current
Drive
I
OH
V
OH
= 2.7V
-1
mA
Sink
I
OL
V
OL
= 0.3V
4
-
mA
High-drive Port
Output Current
P1.5 ~ P1.7
Drive
I
OH
V
OH
= 2.7V
-4
-
mA
