Preliminary W928C73
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System Clock
1/4
TR0 = TCON.4
INT0 = P3.2
GATE = TMOD.3
TL0
TH0
Interrrpt
TF0
C/T = TMOD.2
Interrrpt
TF1
TR1 = TCON.6
Mode 3 of Timer 0 & 1
Watchdog Timer
The watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. When the time out occurs a request flag is
set, which can cause an interrupt or a system reset depend on the EWDI or EWT enable SFR. The
interrupt and reset functions are independent of each other and may be used separately or together
depending on the users software. The watchdog timer should first be restarted by using RWT. This
ensures that the timer starts from a known state.
L_Clock
Divider1
Fosc/8192
Fosc=76.8KHz
9.375Hz
WD1~0
Selector
WDIF
RWT
WD1 WD0
Interrupt
4.64
Hz
2.34
Hz
1.17
Hz
0.59
Hz
0.29
HZ
0.15
Hz
0.07
Hz
0.04
Hz
EWDI
512 clock
delay
EWT
WTRF
Reset
divider2
WDIF:D8.3H
EWT:D8.1H
RWT:D8.0H
WTRF:D8.2H
EWDI:E8.4H
WD1, WD0:8E.7H, 8E.6H
Buzzer Timer
The W928C73 provides a buzzer timer. The buzzer timer can output a single tone signal to the BUZ
pin that frequency range from 150Hz to 38400 Hz.
The operation of buzzer timer is as following. First set the proper value of tone0 then set the ENBUZ
to 1, the uC will output the corresponding frequency (50% duty cycle) to P1.6/BUZ output pin. The
timer can also generate different duty cycle to control the buzzer volume.