LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 61 of 125
When the master is sleeping (idle mode), the following actions happen:
1.
The slave indicates the master that is ready to send data by activating
SPI_SRDY
2.
When the master becomes ready to send, it signalizes this by activating
SPI_MRDY
3.
The master activates the clock and the two processors exchange the communication header and data
4.
If the data has been exchanged, the slave deactivates
SPI_SRDY
to process the received information. The
master does not need to de-assert
SPI_MRDY
as it controls the
SPI_SCLK
5.
After the preparation, the slave activates again
SPI_SRDY
and wait for
SPI_SCLK
activation. When the clock
is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of
the headers), the process will repeat from step 3
Master initiated transfer with a sleeping slave
Figure 33: Data transfer initiated by application processor (master) with a sleeping LISA-U1 series module (slave)
When the slave is sleeping (idle mode), the following actions happen:
1.
The Master wakes the slave by setting the
SPI_MRDY
line active
2.
As soon as the slave is awake, it signals it by activating
SPI_SRDY
3.
The master activates the clock and the two processors exchange the communication header and data
4.
If the data has been exchanged, the slave deactivates
SPI_SRDY
to process the received information. The
master does not need to de-assert
SPI_MRDY
as it controls the
SPI_SCLK
5.
After the preparation, the slave activates again
SPI_SRDY
and wait for
SPI_SCLK
activation. When the clock
is active, all data is transferred without intervention. If there is more data to transfer (flag set in any of the
headers), the process will repeat from step 3
Slave ended transfer
Figure 34: Data transfer terminated and then restarted by LISA-U1 series module (slave)
Starting from the state where data transfer is ongoing, the following actions will happen:
SPI_MRDY
SPI_SRDY
DATA EXCHG
5
2
1
Header
Data
3
4
SPI_MRDY
SPI_SRDY
DATA EXCHG
1
2
4
5
Header
Data
Header
3
