LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 60 of 125
SPI_MRDY
SPI_SRDY
DATA_EXCHANGE
SPI_MOSI
SPI_MISO
Header
Data
SPI_SCLK
Figure 31: IPC Data Flow: SPI_MRDY and SPI_SRDY line usage combined with the SPI protocol
For the correct implementation of the SPI protocol, the frame size is known by both sides before a packet
transfer of each packet. The frame is composed by a header with fixed size (always 4 bytes) and a payload with
variable length (must be a multiple of 4 bytes).
The same amount of data is exchanged in both directions simultaneously. Both sides set their readiness lines
(
SPI_MRDY
/
SPI_SRDY
) independently when they are ready to transfer data. For the correct transmission of the
data the other side must wait for the activating interrupt to allow the transfer of the other side.
The master starts the clock shortly after
SPI_MRDY
and
SPI_SRDY
are set to active. The number of clock
periods sent by the master is exactly that one of the frame-size to be transferred. The
SPI_SRDY
line will be set
low after the master sets the clock line to idle state. The
SPI_MRDY
line is also set inactive after the clock line is
set idle, but in case of a big transfer containing multiple packets, the
SPI_MRDY
line stays active.
1.9.4.2
IPC communication and power saving
If power saving is enabled by AT command (AT+UPSV=1 or AT+UPSV=2), the LISA-U1 series module
automatically enters idle mode when the master indicates that it is not ready to transmit or receive by the
SPI_MRDY
signal, or when the LISA-U1 series module itself doesn’t transfer data.
1.9.4.3
IPC communication examples
In the following, three IPC communication scenarios are described:
Slave initiated data transfer, with a sleeping master
Master initiated data transfer, with a sleeping slave
Slave ended data transfer
Slave initiated transfer with a sleeping master
Figure 32: Data transfer initiated by LISA-U1 series module (slave), with a sleeping application processor (master)
SPI_MRDY
SPI_SRDY
DATA EXCHG
2
4
5
Header
Data
Header
3
1