LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 51 of 125
AT+UPSV=2: power saving enabled and controlled by the RTS line
If the
RTS
line is set to OFF by the DTE the module is allowed to enter idle-mode as for UPSV=1 case. Instead,
the UART is disabled as long as
RTS
line is set to OFF.
If the
RTS
line is set to ON by the DTE the module is not allowed to enter idle-mode and the UART is kept
enabled until the
RTS
line is set to OFF.
When an OFF-to-ON transition occurs on the
RTS
input line, the UART is re-enabled and the module switches
from idle-mode to active-mode in 20 ms. This configuration can only be enabled with the module HW flow
control disabled.
Since HW flow control is disabled, the
CTS
line is always set to ON by the module.
When the
RTS
line is set to OFF by the DTE, the timeout to enter idle-mode from the last data received
at the serial port during the active-mode is the one previously set with the AT+UPSV=1 configuration or
it is the default value.
If the module must transmit some data (e.g. URC), the UART is temporarily enabled even if the
RTS
line
is set to OFF; UART wake-up in case of
RTS
line set to OFF is also possible via data reception (as
described in the following).
If the USB is connected and active, the module is forced to stay in active-mode, theUPSV=1 and
+UPSV=2 modes are overruled, but in any case they have effect on the UART behavior (they configure
UART power saving mode, when it is enabled/disabled).
Wake up from idle-mode to active-mode via data reception
If data is transmitted by the DTE during the module idle-mode, it will be lost (not correctly received by the
module) in the following cases:
+UPSV=1 with hardware flow control disabled
+UPSV=2 with hardware flow control disabled and RTS line set to OFF
When the module is in idle-mode, the
TxD
input line of the module is always configured to wake up the module
from idle-mode to active-mode via data reception: when a low-to-high transition occurs on the
TxD
input line, it
causes the wake-up of the system. The module switches from idle-mode to active-mode within 20 ms from the
first data reception: this is the “wake up time” of the module. As a consequence, the first character sent when
the module is in idle-mode (i.e. the wake up character) won’t be a valid communication character because it
can’t be recognized, and the recognition of the subsequent characters is guaranteed only after the complete
wake-up (i.e. after 20 ms).
Figure 25 and Figure 26 show an example of common scenarios and timing constraints:
HW flow control set in the DCE, and no HW flow control set in the DTE, needed to see the
CTS
line
changing on DCE
Power saving configuration is active and the timeout from last data received to idle-mode start is set to 2000
frames (AT+UPSV=1,2000)
Figure 25 shows the case where DCE is in idle mode and a wake-up is forced. In this scenario the only character
sent by the DTE is the wake-up character; as a consequence, the DCE will return to idle-mode when the timeout
from last data received expires. (2000 frames without data reception).
