LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 62 of 125
1.
In case of the last transfer, the master will lower its
SPI_MRDY
line. After the data-transfer is finished the
line must be low. If the slave has already set its
SPI_SRDY
line, the master must raise its line to initiate the
next transfer (slave-waking-procedure)
2.
If the data has been exchanged, the slave will deactivate
SPI_SRDY
to process the received information. This
is the normal behavior
3.
The slave will indicate the master that is ready to send data by activating
SPI_SRDY
4.
When the master is ready to send, it will signalize this by activating
SPI_MRDY
. This is optional, when
SPI_MRDY
is low before
5.
The slave indicates immediately after a transfer termination that it is ready to start transmission again. In this
case the slave will raise
SPI_SRDY
again. The
SPI_MRDY
line can be either high or low: the master has only
to ensure that the
SPI_SRDY
change will be detected correctly via interrupt
For more details regarding IPC communication protocol please refer to
SPI Application Note
1.9.4.4
IPC application circuit
SPI_MOSI
is the data line input for the module since it runs as SPI slave: it must be connected to the data line
output (MOSI) of the application processor that runs as an SPI master.
SPI_MISO
is the data line output for the module since it runs as SPI slave: it must be connected to the data line
input (MISO) of the application processor that runs as an SPI master.
SPI_SCLK
is the clock input for the module since it runs as SPI slave: it must be connected to the clock line
output (SCLK) of the application processor that runs as an SPI master.
SPI_MRDY
is an input for the module able to detect an external interrupt which comes from the application
processor.
SPI_SRDY
is an output for the module, and the application processor should be able to detect an external
interrupt which comes from the module on its connected pin.
Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when
the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity.
LISA-U1 series
(SPI slave)
MOSI
Application Processor
(SPI master)
MISO
SCLK
Interrupt
GPIO
GND
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
Figure 35: IPC Interface application circuit
If direct access to the USB or the UART interfaces of the module is not provided, it is recommended to
provide direct access to the
SPI_MOSI
,
SPI_MISO
,
SPI_SCLK
,
SPI_MRDY
,
SPI_SRDY
lines of the
module for debug purpose: testpoints can be added on the lines to accommodate the access and a 0
Ω
series resistor must be mounted on each line to detach the module pin from any other connected
device.
If the SPI/IPC interface is not used, the
SPI_MOSI
,
SPI_MISO
,
SPI_SCLK
,
SPI_MRDY
,
SPI_SRDY
pins
can be left unconnected.
