SECTION 3
CIM PROTOCOL
PM055 Rev 2 00/08/31
Thomson Technology
50
Unfortunately due to processing limitations response packets from the CIM to the host
can have up to 25ms gaps in the data. The CIM response data is shifted out in 16
character increments, in some cases it can take up to 25 ms to shift out the next 16
character buffer.
The host pre-transmit delay is the minimum time required between the reception of the
last byte of a frame (response) and the transmission of the first byte of a new frame
(request). The following values show the necessary pre-transmit delays to insure reliable
transmission of data to the CIM.
baudrate
delay(ms)
1200 130
2400 80
4800 40
9600 30
14400 30
19200 30
The typical CIM, MEC 20 and TSC 800 data is accessible through direct register read
and writes. Programming the CIM is done using the same protocol with the CIM ID
instead of the MEC ID.
4.
Preset Multiple Registers (Type 16)
The preset multiple registers packet is used to write specific values to the controllers.
Numeric values are shown in hexidecimal.
Preset Multiple Registers Request
The packet format for this request is shown below.
ss 10 aaaa pppp bb rrrr . . . . rrrr
cccc
ss
MEC 20 ID (00 to FF)
aaaa
Starting register (4aaaa)
pppp
Register count (number of points)
bb
Содержание CIM 3.0
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