Texas Instruments TVP4020 PERMEDIA 2, Справочное руководство

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TVP4020
Programmers Reference Manual
Programming Model
11
Render (PERMEDIA_TRAPEZOID_PRIMITIVE);
}
The InFIFOSpace FIFO control register contains a count of the number
of entries currently free in the FIFO. The chip increments this register for
each entry it removes from the FIFO and decrements it every time the
host puts an entry in the FIFO. Before writing to the input FIFO, the user
must check that there is sufficient space by reading the InFIFOSpace
register.
The Graphics Core FIFO interface provides a port through which both
GC register addresses and data can be sent to the input FIFO. A range
of 4 Kbytes of host space is provided although all data may be sent
through one address in the range. ALL accesses go directly to the FIFO;
the range is provided to allow for data transfer schemes which force the
use of incrementing addresses.
Note that the GC registers cannot be read through this interface.
Command buffers generated to be sent to the input FIFO interface, may
be read directly by P
ERMEDIA
by using the DMA controller.
A data formatting scheme is provided to allow for multiple data words to
be sent with one address word where adjacent or grouped registers are
being written, or where one register is to be written many times.
Note. The FIFO interface can be accessed at 32 bit boundaries. This is
to allow a direct copy from a DMA format buffer.
3.2.4 The DMA Interface
Loading registers directly via the FIFO is often an inefficient way to
download data to P
ERMEDIA
. Given that the FIFO can accommodate only
a small number of entries, P
ERMEDIA
has to be frequently interrogated to
determine how much space is left. Also, consider the situation where a
given API function requires a large amount of data to be sent to
P
ERMEDIA
. If the FIFO is written directly then a return from this function is
not possible until almost all the data has been consumed by P
ERMEDIA
.
This may take some time depending on the types of primitives being
drawn.
To avoid these problems P
ERMEDIA
provides an on-chip DMA controller
which can be used to load data from arbitrary sized (< 64K 32-bit words)
host buffers into the FIFO. In its simplest form the host software has to
prepare a host buffer containing register address tag descriptions and
data values. It then writes the base address of this buffer to the
DMAAddress register and the count of the number of words to transfer
to the DMACount register. Writing to the DMACount register starts the
DMA transfer and the host can now perform other work. In general, if the
complete set of rendering commands required by a given call to a driver