TVP4020
Programmers Reference Manual
Graphics Programming
127
This to allow low level resynchronization between the graphics core and
PCI clock domains. The FIFO has an extra bit in width to accommodate
the interrupt signal. When both the data and tag are written into the
FIFO, only the first entry in the FIFO will cause the interrupt (assuming
an interrupt was requested).
The remaining bits in the Sync data field are free and can be used by the
host to identify the reason for the Sync.
5.15.4
Registers
Filtering is controlled by the FilterMode register:
0
8
16
24
31
Reserved
Individual bits defined above
Figure 5.50
FilterMode Register
Statistic collection is controlled by the StatisticMode register:
0
8
16
24
31
Reserved
Enable Statistics
Statistics Type
Monitor Culled Fragments
Compare Function
Include Spans
Monitor Pixels Written
Figure 5.51
StatisticMode Register
The Include Spans bit allows control over whether or not block fills are
included in the returned information.
0
8
16
24
31
Reserved
Pick Flag
Figure 5.52
PickResult Register
ResetPickResult is used to clear the pick flag. The data field for this
register is unused.
Содержание TVP4020 PERMEDIA 2
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