TVP4020
Programmers Reference Manual
Initialization
131
6.2.2
Memory Configuration
The memory interface control registers should be programmed to reflect
the type and amount of memory fitted. The registers are specified in the
TVP4020 Hardware Reference Manual.
6.2.3
SVGA and Internal Video Timing Registers
Details for programming the SVGA registers can be found in the
TVP4020 Hardware Reference Manual.
The core video timing generator should be programmed to reflect the
timings of the monitor being used and the screen resolution and color
depth. Note that there is also a SVGA VTG and care must be taken to
ensure the correct one is enabled at the right time. To change from
SVGA to core display mode, two stages are required. Firstly the core
VTG must be set-up and then VGAControlReg must be loaded (the
EnableVGADisplay bit set to 0).
Details of programming the registers for both VTGs can be found in the
TVP4020 Hardware Reference Manual.
6.2.4
Screen Width
The width of the screen is initialized by setting the three partial products
fields in the FBReadMode, LBReadMode and TextureMapFormat
registers. Note that the width is in pixels, not in bytes, so the same
values apply regardless of framebuffer depth, for a given screen
resolution. A full list is given in Appendix C.
To initialize the screen to be 1024 pixels wide the registers would be set
as follows.
fbReadMode.PP0 = 5
fbReadMode.PP1 = 5
fbReadMode.PP2 = 0
FBReadMode(fbReadMode)
lbReadMode.PP0 = 5
lbReadMode.PP1 = 5
lbReadMode.PP2 = 0
LBReadMode(lbReadMode)
textureMapFormat.PP0 = 5
textureMapFormat.PP1 = 5
textureMapFormat.PP2 = 0
TextureMapFormat(textureMapFormat)
Содержание TVP4020 PERMEDIA 2
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