TVP4020
Programmers Reference Manual
Programming Model
9
updated for almost every primitive whereas other control registers such
as those for scissor clip or logical ops can be updated much less
frequently. Pre-loading of the appropriate control registers can reduce
the amount of data that has to be loaded into the chip for a given
primitive thus improving efficiency. In addition, as described above, the
final values in internal registers can sometimes be used for subsequent
drawing operations.
The tables in Appendix D lists the graphics registers according to their
type, name and address.
3.2
P
ERMEDIA
I/O Interface
There are four ways of loading P
ERMEDIA
registers:
•
The host writes a value to the mapped address of the register
•
The host writes address-tag/data pairs to the FIFO.
•
The host writes address-tag/data pairs to the FIFO via DMA.
•
The host writes to raw memory mapped GP FIFO addresses.
In cases where the host writes data values directly to the chip via the
register file, consideration has to be given to FIFO overflow (unless PCI
Disconnect is enabled). The InFIFOSpace register indicates how many
free entries remain in the FIFO. Before writing to any register, the host
must ensure that there is enough space left in the FIFO. The values in
this register can be read at any time. When using DMA, the DMA
controller will automatically ensure that there is room in the FIFO before
it performs further transfers. Thus a buffer of any size up to 64K, 32 bit
words, can be passed to the DMA controller. The FIFO and DMA
controller are described in more detail below.
3.2.1
PCI Disconnect
The PCI bus protocol incorporates a feature known as PCI Disconnect,
which is supported by P
ERMEDIA
. PCI Disconnect is enabled by writing a
one to bit zero of the DisconnectControl register which is at offset 0x68
in PCI Region 0. Once the P
ERMEDIA
is in this mode, if the host processor
attempts to write to the full FIFO then instead of the write being lost, the
P
ERMEDIA
chip will assert PCI Disconnect which will cause the host
processor to keep retrying the write cycle until it succeeds.
This feature allows faster download of data to P
ERMEDIA
, since the host
need not poll the InFIFOSpace register but should be used with care
since whenever the PCI Disconnect is asserted the bus is effectively
hogged by the host processor until such time as the P
ERMEDIA
frees up
an entry in its FIFO. In general this mode should only be used either for
operations where it is known that the P
ERMEDIA
can consume data faster
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