Texas Instruments MSP430x4xx Family, Руководство пользователя

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MSP430X Extended Instructions
4-45 16-Bit MSP430X CPU
Register Mode Extension Word
The register mode extension word is shown in Figure 4−25 and described in
Table 4−11. An example is shown in Figure 4−27.
Figure 4−25. The Extension Word for Register Modes
15 12 11 10 9 8 7 6 5 4 3 0
0001 1 00 ZC # A/L 0 0 (n−1)/Rn
Table 4−11. Description of the Extension Word Bits for Register Mode
Bit Description
15:11 Extension word op-code. Op-codes 1800h to 1FFFh are extension
words.
10:9 Reserved
ZC Zero carry bit.
0: The executed instruction uses the status of the carry bit C.
1: The executed instruction uses the carry bit as 0. The carry bit will
be defined by the result of the final operation after instruction execu-
tion.
# Repetition bit.
0: The number of instruction repetitions is set by extension-word bits
3:0.
1: The number of instructions repetitions is defined by the value of the
four LSBs of Rn. See description for bits 3:0.
A/L Data length extension bit. Together with the B/W-bits of the following
MSP430 instruction, the AL bit defines the used data length of the
instruction.
A/L B/W Comment
0 0 Reserved
0 1 20-bit address-word
1 0 16-bit word
1 1 8-bit byte
5:4 Reserved
3:0 Repetition Count.
# = 0: These four bits set the repetition count n. These bits contain
n - 1.
# = 1: These four bits define the CPU register whose bits 3:0 set the
number of repetitions. Rn.3:0 contain n - 1.