ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.7.9.3
EMIF Electrical Data and Timing
5.7.9.3.1 Asynchronous RAM
Table 5-36. EMIF Asynchronous Memory Timing Requirements
NO.
MIN
MAX
UNIT
Reads and Writes
E
EMIF clock period
SYSCLK period
ns
Pulse duration, EMxWAIT assertion and
2
t
w(EM_WAIT)
2E
ns
deassertion
Reads
12
t
su(EMDV-EMOEH)
Setup time, EMxD[y:0] valid before EMxOE high
15
ns
13
t
h(EMOEH-EMDIV)
Hold time, EMxD[y:0] valid after EMxOE high
0
ns
Setup Time, EMxWAIT asserted before end of
14
t
su(EMOEL-EMWAIT)
4E
ns
Strobe Phase
(1)
Writes
Setup Time, EMxWAIT asserted before end of
28
t
su(EMWEL-EMWAIT)
4E
ns
Strobe Phase
(1)
(1)
Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states.
and
describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-37. EMIF Asynchronous Memory Switching Characteristics
(1) (2) (3)
NO.
PARAMETER
MIN
MAX
UNIT
Reads and Writes
1
t
d(TURNAROUND)
Turn around time
(TA)*E–3
(TA)*E+2
ns
Reads
EMIF read cycle time (EW = 0)
(RS+RST+RH+2)*E–3
(RS+RST+RH+2)*E+2
ns
3
t
c(EMRCYCLE)
(RS+RST+RH+2+
(RS+RST+RH+2+
EMIF read cycle time (EW = 1)
ns
(EWC*16))*E–3
(EWC*16))*E+2
Output setup time, EMxCS[y:2] low
(RS)*E–3
(RS)*E+2
ns
to EMxOE low (SS = 0)
4
t
su(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
–3
2
ns
to EMxOE low (SS = 1)
Output hold time, EMxOE high to
(RH)*E–3
(RH)*E
ns
EMxCS[y:2] high (SS = 0)
5
t
h(EMOEH-EMCEH)
Output hold time, EMxOE high to
–3
0
ns
EMxCS[y:2] high (SS = 1)
Output setup time, EMxBA[y:0]
6
t
su(EMBAV-EMOEL)
(RS)*E–3
(RS)*E+2
ns
valid to EMxOE low
Output hold time, EMxOE high to
7
t
h(EMOEH-EMBAIV)
(RH)*E–3
(RH)*E
ns
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
8
t
su(EMAV-EMOEL)
(RS)*E–3
(RS)*E+2
ns
to EMxOE low
Output hold time, EMxOE high to
9
t
h(EMOEH-EMAIV)
(RH)*E–3
(RH)*E
ns
EMxA[y:0] invalid
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual
) for more
information.
(2)
E = EMxCLK period in ns.
(3)
EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual
) for more information.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
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