ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
Table 4-1. Signal Descriptions (continued)
TERMINAL
ZWT
PTP
PZP
I/O/Z
DESCRIPTION
MUX
NAME
BALL
PIN
PIN
POSITION
NO.
NO.
NO.
RESET
Device Reset (in) and Watchdog Reset (out). The
devices have a built-in power-on reset (POR) circuit.
During a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset occurs. During watchdog
reset, the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. A resistor between
2.2 k
Ω
and 10 k
Ω
should be placed between XRS and
V
DDIO
. If a capacitor is placed between XRS and V
SS
for
XRS
F19
124
69
I/OD
noise filtering, it should be 100 nF or smaller. These
values will allow the watchdog to properly drive the XRS
pin to V
OL
within 512 OSCCLK cycles when the
watchdog reset is asserted. Regardless of the source, a
device reset causes the device to terminate execution.
The program counter points to the address contained at
the location 0x3F FFC0. When reset is deactivated,
execution begins at the location designated by the
program counter. The output buffer of this pin is an
open-drain with an internal pullup. (
↑
)
CLOCKS
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
X1
G19
123
68
I
this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
On-chip crystal-oscillator output. A quartz crystal may be
X2
J19
121
66
O
connected across X1 and X2. If X2 is not used, it must
be left unconnected.
NO CONNECT
No connect. BGA ball is electrically open and not
NC
H4
–
–
connected to the die.
JTAG
TCK
V15
81
50
I
JTAG test clock with internal pullup (see
JTAG test data input (TDI) with internal pullup. TDI is
TDI
W13
77
46
I
clocked into the selected register (instruction or data) on
a rising edge of TCK.
JTAG scan out, test data output (TDO). The contents of
TDO
W15
78
47
O/Z
the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK.
JTAG test-mode select (TMS) with internal pullup. This
TMS
W14
80
49
I
serial control input is clocked into the TAP controller on
the rising edge of TCK.
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode,
and the test reset signals are ignored. NOTE: TRST is
an active-low test pin and must be maintained low at all
times during normal device operation. An external
TRST
V14
79
48
I
pulldown resistor is required on this pin. The value of this
resistor should be based on drive strength of the
debugger pods applicable to the design. A 2.2-k
Ω
resistor generally offers adequate protection. Because
the value of the resistor is application-specific, TI
recommends that each target board be validated for
proper operation of the debugger and the application.
This pin has an internal 50-ns (nominal) glitch filter.
36
Terminal Configuration and Functions
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