ADV
ANCEINFORMA
TION
Inactive
Device Active
CPU1 IDLE
Instruction
Enabled
Bypassed &
Powered -Down
On
Powered Down
Powering up
On
HIBERNATE
CPU1 Boot ROM
Device Status
INTOSC1,INTOSC2,
X1/X2
GPIOHIBWAKEn,
XRSn
PLLs
I/O Isolation
IoRestore() or Application Specific Operation
CPU1 HIB
config
(A)
(B)
(C)
(D)
tw(HIBWAKEn),
tw(XRSn)
(F)
(G)(H)
(I)(J)
XCLKCOUT
Application Specific Operation
Application SpecificOperation
(E)
td(IDLE-XCOS)
Td(WAKE-HIB)
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
A.
CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if
using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank,
USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the
PLL and peripheral clocks before entering HIBERNATE.
B.
IDLE instruction is executed to put the device into HIBERNATE mode.
C.
The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained.
CPU1 is powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash
are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their
memory contents lost.
D.
A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2,
and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of
these clock sources.
E.
After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of
the remainder of the device.
F.
The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the
CPU1.REC.HIBRESETn bit. After the OTP trims are loaded, the BootROM code will branch to the user-defined
IoRestore function if it has been configured.
G.
At this point, the device is out of HIBERNATE mode, and the application may continue.
H.
The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O
isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the
application requirements.
I.
If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will
disable I/O isolation automatically if it was not taken care of inside of IoRestore.
J.
BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the "ROM Code and Peripheral
Booting" chapter of the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual
(
) for more
information.
Figure 5-17. HIBERNATE Entry and Exit Timing Diagram
NOTE
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue
its execution to boot as determined by the HIBBOOTMODE register. Refer to the "ROM
Code and Peripheral Booting" chapter of the
TMS320F2837xS Delfino Microcontrollers
Technical Reference Manual
(
) for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function.
Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is
not defined, the BootROM will automatically disable isolation before booting as
determined by the HIBBOOTMODE register.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
81
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