Terasic TR10a-HL, Руководство пользователя

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QDRIIF_Q9 Read Data bus[9] 1.8-V HSTL Class I PIN_W11
QDRIIF_Q10 Read Data bus[10] 1.8-V HSTL Class I PIN_V10
QDRIIF_Q11 Read Data bus[11] 1.8-V HSTL Class I PIN_W10
QDRIIF_Q12 Read Data bus[12] 1.8-V HSTL Class I PIN_W9
QDRIIF_Q13 Read Data bus[13] 1.8-V HSTL Class I PIN_Y13
QDRIIF_Q14 Read Data bus[14] 1.8-V HSTL Class I PIN_Y14
QDRIIF_Q15 Read Data bus[15] 1.8-V HSTL Class I PIN_AL10
QDRIIF_Q16 Read Data bus[16] 1.8-V HSTL Class I PIN_AM9
QDRIIF_Q17 Read Data bus[17] 1.8-V HSTL Class I PIN_AN6
QDRIIF_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I PIN_AB10
QDRIIF_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I PIN_AB9
QDRIIF_K_p Clock P
Differential 1.8-V
HSTL Class I
PIN_AE9
QDRIIF_K_n
Clock N
Differential 1.8-V
HSTL Class I
PIN_AD9
QDRIIF_CQ_p Echo clock P 1.8-V HSTL Class I PIN_AM8
QDRIIF_CQ_n
Echo clock N
1.8-V HSTL Class I PIN_AM7
QDRIIF_RPS_n
Report Select
1.8-V HSTL Class I PIN_AB13
QDRIIF_WPS_n
Write Port Select
1.8-V HSTL Class I PIN_AB14
QDRIIF_DOFF_n PLL Turn Off 1.8-V HSTL Class I PIN_AB12
QDRIIF_ODT On-Die Termination Input 1.8-V HSTL Class I PIN_AE14
QDRIIF_QVLD
ValidOutput Indicator
1.8-V HSTL Class I PIN_AL9
2.9 QSPF+ Ports
The development board has four independent 40G QSFP+ connectors that use one
transceiver channel each from the Arria 10 GX FPGA device. These modules take in
serial data from the Arria 10 GX FPGA device and transform them to optical signals.
The board includes cage assemblies for the QSFP+ connectors. Figure 2-12 shows the
connections between the QSFP+ and Arria 10 GX FPGA.