Terasic TR10a-HL, Руководство пользователя

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QDRIIA_D15 Write data bus[15] 1.8-V HSTL Class I PIN_E9
QDRIIA_D16 Write data bus[16] 1.8-V HSTL Class I PIN_E11
QDRIIA_D17 Write data bus[17] 1.8-V HSTL Class I PIN_E8
QDRIIA_Q0 Read Data bus[0] 1.8-V HSTL Class I PIN_P13
QDRIIA_Q1 Read Data bus[1] 1.8-V HSTL Class I PIN_R13
QDRIIA_Q2 Read Data bus[2] 1.8-V HSTL Class I PIN_N13
QDRIIA_Q3 Read Data bus[3] 1.8-V HSTL Class I PIN_M14
QDRIIA_Q4 Read Data bus[4] 1.8-V HSTL Class I PIN_M12
QDRIIA_Q5 Read Data bus[5] 1.8-V HSTL Class I PIN_K13
QDRIIA_Q6 Read Data bus[6] 1.8-V HSTL Class I PIN_K12
QDRIIA_Q7 Read Data bus[7] 1.8-V HSTL Class I PIN_K14
QDRIIA_Q8 Read Data bus[8] 1.8-V HSTL Class I PIN_J14
QDRIIA_Q9 Read Data bus[9] 1.8-V HSTL Class I PIN_H12
QDRIIA_Q10 Read Data bus[10] 1.8-V HSTL Class I PIN_H11
QDRIIA_Q11 Read Data bus[11] 1.8-V HSTL Class I PIN_G10
QDRIIA_Q12 Read Data bus[12] 1.8-V HSTL Class I PIN_L14
QDRIIA_Q13 Read Data bus[13] 1.8-V HSTL Class I PIN_L12
QDRIIA_Q14 Read Data bus[14] 1.8-V HSTL Class I PIN_M13
QDRIIA_Q15 Read Data bus[15] 1.8-V HSTL Class I PIN_N12
QDRIIA_Q16 Read Data bus[16] 1.8-V HSTL Class I PIN_R14
QDRIIA_Q17 Read Data bus[17] 1.8-V HSTL Class I PIN_T14
QDRIIA_BWS_n0 Byte Write select[0] 1.8-V HSTL Class I PIN_B13
QDRIIA_BWS_n1 Byte Write select[1] 1.8-V HSTL Class I PIN_C13
QDRIIA_K_P Clock P
Differential 1.8-V HSTL
Class I
PIN_F12
QDRIIA_K_N Clock N
Differential 1.8-V HSTL
Class I
PIN_E12
QDRIIA_CQ_P Echo clock P 1.8-V HSTL Class I PIN_J13
QDRIIA_CQ_N Echo clock N 1.8-V HSTL Class I PIN_H13
QDRIIA_RPS_n Report Select 1.8-V HSTL Class I PIN_U9
QDRIIA_WPS_n Write Port Select 1.8-V HSTL Class I PIN_U8
QDRIIA_DOFF_n DLL enable 1.8-V HSTL Class I PIN_R9
QDRIIA_ODT
On-Die Termination
Input
1.8-V HSTL Class I PIN_T10
QDRIIA_QVLD Valid Output 1.8-V HSTL Class I PIN_R12
Table 2-12 QDRII+ SRAM B Pin Assignments, Schematic Signal Names, and