32
QDRIID_Q17
Read Data bus[17]
1.8-V HSTL Class I
PIN_P28
QDRIID_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I
PIN_C37
QDRIID_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I
PIN_F37
QDRIID_K_p
Clock P
Differential 1.8-V
HSTL Class I
PIN_F32
QDRIID_K_n
Clock N
Differential 1.8-V
HSTL Class I
PIN_E32
QDRIID_CQ_p
Echo clock P
1.8-V HSTL Class I
PIN_G35
QDRIID_CQ_n
Echo clock N
1.8-V HSTL Class I
PIN_F35
QDRIID_RPS_n
Report Select
1.8-V HSTL Class I
PIN_V33
QDRIID_WPS_n
Write Port Select
1.8-V HSTL Class I
PIN_V32
QDRIID_DOFF_n
PLL Turn Off
1.8-V HSTL Class I
PIN_W31
QDRIID_ODT
On-Die Termination Input
1.8-V HSTL Class I
PIN_Y33
QDRIID_QVLD
ValidOutput Indicator
1.8-V HSTL Class I
PIN_P31
Table 2-15 QDRII+ SRAM E Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description
I/O Standard
Arria 10 GX
Pin Number
QDRIIE_A0
Address bus[0]
1.8-V HSTL Class I
PIN_BB9
QDRIIE_A1
Address bus[1]
1.8-V HSTL Class I
PIN_BB8
QDRIIE_A2
Address bus[2]
1.8-V HSTL Class I
PIN_AW15
QDRIIE_A3
Address bus[3]
1.8-V HSTL Class I
PIN_AW14
QDRIIE_A4
Address bus[4]
1.8-V HSTL Class I
PIN_AW13
QDRIIE_A5
Address bus[5]
1.8-V HSTL Class I
PIN_AY13
QDRIIE_A6
Address bus[6]
1.8-V HSTL Class I
PIN_AY14
QDRIIE_A7
Address bus[7]
1.8-V HSTL Class I
PIN_BA14
QDRIIE_A8
Address bus[8]
1.8-V HSTL Class I
PIN_BA12
QDRIIE_A9
Address bus[9]
1.8-V HSTL Class I
PIN_BB12
QDRIIE_A10
Address bus[10]
1.8-V HSTL Class I
PIN_AU13
QDRIIE_A11
Address bus[11]
1.8-V HSTL Class I
PIN_AV13
QDRIIE_A12
Address bus[12]
1.8-V HSTL Class I
PIN_AY11
QDRIIE_A13
Address bus[13]
1.8-V HSTL Class I
PIN_BA11
QDRIIE_A14
Address bus[14]
1.8-V HSTL Class I
PIN_AK14
QDRIIE_A15
Address bus[15]
1.8-V HSTL Class I
PIN_AM13
QDRIIE_A16
Address bus[16]
1.8-V HSTL Class I
PIN_AN13
Содержание TR10a-HL
Страница 1: ...1...
Страница 3: ...3...
Страница 71: ...71 Figure 5 14 Si5340A Demo Figure 5 15 Si5340B Demo...
Страница 82: ...82 Figure 6 3 Progress and Result Information for the QDRII Demonstration...
Страница 107: ...107...
Страница 111: ...111 Figure 8 5QSFP Transceiver Loopback Test in Progress Figure 8 6QSFP Transceiver Loopback Done...