Terasic TR10a-HL, Руководство пользователя

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QDRIIE_Q13 Read Data bus[13] 1.8-V HSTL Class I PIN_AV15
QDRIIE_Q14 Read Data bus[14] 1.8-V HSTL Class I PIN_BA15
QDRIIE_Q15 Read Data bus[15] 1.8-V HSTL Class I PIN_AW16
QDRIIE_Q16 Read Data bus[16] 1.8-V HSTL Class I PIN_AY16
QDRIIE_Q17 Read Data bus[17] 1.8-V HSTL Class I PIN_AY17
QDRIIE_BWS_n0
Byte Write select[0]
1.8-V HSTL Class I PIN_AM17
QDRIIE_BWS_n1
Byte Write select[1]
1.8-V HSTL Class I PIN_AM19
QDRIIE_K_p Clock P
Differential 1.8-V
HSTL Class I
PIN_AP18
QDRIIE_K_n Clock N
Differential 1.8-V
HSTL Class I
PIN_AR18
QDRIIE_CQ_p
Echo clock P
1.8-V HSTL Class I PIN_AV16
QDRIIE_CQ_n
Echo clock N
1.8-V HSTL Class I PIN_AV17
QDRIIE_RPS_n Report Select 1.8-V HSTL Class I PIN_BD10
QDRIIE_WPS_n Write Port Select 1.8-V HSTL Class I PIN_BC10
QDRIIE_DOFF_n PLL Turn Off 1.8-V HSTL Class I PIN_BD11
QDRIIE_ODT
On-Die Termination Input
1.8-V HSTL Class I PIN_BB13
QDRIIE_QVLD
ValidOutput Indicator
1.8-V HSTL Class I PIN_AR17
Table 2-16 QDRII+ SRAM F Pin Assignments, Schematic Signal Names, and
Functions
Schematic
Signal Name
Description I/O Standard
Arria 10 GX
Pin Number
QDRIIF_A0 Address bus[0] 1.8-V HSTL Class I PIN_AG14
QDRIIF_A1 Address bus[1] 1.8-V HSTL Class I PIN_AF14
QDRIIF_A2 Address bus[2] 1.8-V HSTL Class I PIN_AJ13
QDRIIF_A3 Address bus[3] 1.8-V HSTL Class I PIN_AK13
QDRIIF_A4 Address bus[4] 1.8-V HSTL Class I PIN_AH13
QDRIIF_A5 Address bus[5] 1.8-V HSTL Class I PIN_AG13
QDRIIF _A6 Address bus[6] 1.8-V HSTL Class I PIN_AG12
QDRIIF_A7 Address bus[7] 1.8-V HSTL Class I PIN_AH12
QDRIIF_A8 Address bus[8] 1.8-V HSTL Class I PIN_AM12
QDRIIF_A9 Address bus[9] 1.8-V HSTL Class I PIN_AN12
QDRIIF_A10 Address bus[10] 1.8-V HSTL Class I PIN_AE12
QDRIIF_A11 Address bus[11] 1.8-V HSTL Class I PIN_AF12
QDRIIF_A12 Address bus[12] 1.8-V HSTL Class I PIN_AK12