Teledyne ADFM Analog Output Module, Техническое руководство, Страница: 71 / 156

ADFM System Overview
SYSTEM-BUS
TIMING GEN.-BUS RCVR-BUS
*
A
D
AD
C
A
D
AD
C
1
RC
V
-
XFM
R
RCV
-
AM
P
M
IXE
R
L
PF
LIM
ITER
FIFO
C
O
R
R
E
LA
T
O
R
BU
S-
INTFC
CP
U
OF
B
-I
O
R
S
SI
-L
PF
RSS
I-
BUFF
CU
RR
-
XF
M
R
XM
T-
XFM
R
XM
T
-A
M
P
IS-
B
AR
R
IER
(
O
pti
onal
)
IS-
B
AR
R
IE
R
(
O
pt
ional)
BU
S
-
IN
TFC
BU
S
-
IN
TFC
MO
D-
IN
TFC
R
E
CR
D.
R
S
-422
TELC
O
VX
M
T
VD
C
VD
D1
TIM
ING
-G
EN
LO TEST-SIG
XM
T-SIG
RC
V-
SIG
XM
T-
SIG
RS
-2
3
2
FP
-INTFC
TP59
R
SSI
0 -
2
.50V
TP
5
1
50mV/mA
XD
CR-
SER
. D
A
T
A IN
IS-BAR
RIER
DC
-PO
W
ER E
N
TR
Y
M
A
IN
S PO
WE
R
ENTR
Y
MA
IN
S
1
1
5/2
3
0 V
a
c
EXT-D
C
24
-4
8 Vdc
INT-B
A
TTE
R
Y
24
V
d
c
PWR
FIL
TE
R
DC
DC
AU
X
-
RE
G
DC
DC
DC
/D
C-
CO
NV
R
C
V PW
R-
STR
O
B
E
M
A
IN
PWR
-
CO
NTR
O
L
XD
CR
P
W
R-
STR
O
B
E
DC
DC
RE
F
E
RE
NC
E
DC
DC
XDC
R
PW
R-
RE
GU
L
A
T
O
R
XD
CR P
W
R-
FIL
T
ER
XM
T
PW
R
-
FIL
T
ER
V
RCV
7.9V
TP
6
VXM
T
7.9V
TP5
VR
1
2.50V
TP4
VC
C
+5V
TP
1
VD
D1
+5V
TP3
VD
D3
+16V
TP
2
VDD
2
+5
V
TP7
VD
C
TP71
I(-)
TP70
I(+
)
0.1R
CPU-BUS
Figure A-1. Electronics Unit Block Diagram
ADFM Technical Manual (January 2000) page A-7