Supero SuperServer 5012B-6, Руководство пользователя

Страница: 84 / 112

7-10
S
UPER
S
ERVER 5012B-6/5012B-E Manual
Active to Precharge Delay
This item regulates the number of memory clock cycles allowed for memory
refresh charging. The options are " 7 ", "6" and "5". Shorter timings increase
system memory throughput at the risk of lacking sufficient refresh charge.
DRAM RAS# to CAS# Delay
This item regulates the number of memory closk cycles between strobing a
row address (RAS) and a column address (CAS). Shorter numbers of clock
cycles improve system memory performance at the risk of missing data.
The options are " 3 " and "2".
DRAM RAS Precharge
This item regulates the number of system memory clock cycles for RAS
precharging. The options are " 3 " and "2".
DRAM Data Integrity Mode
This item regulates CPU access to the data stored in the protected area of
dynamic random access memory (DRAM) on the motherboard. To preserve
its integrity, critical system information is usually stored in a protected area
of memory. If set to the "ECC" mode, the CPU will have access to data
stored in the area when performing ECC (Error Correction/Checking)
activities. The options are "ECC" and " Non-ECC ".
Memory Frequency For
This item regulates system memory frequency. The options are "PC100",
"PC133" and " Auto ".
DRAM Read Thermal Management
This item regulates the system's ability to read system thermal data. The
options are " Disabled " and "Enabled".