Operating Instructions
IS1 PROFIBUS 3.00 E
- Technical alterations reserved -
95
PROFIBUS DP interface for IS1+
3.7 Group alarm / field station status
1 byte input data (status register) and 1 byte output data (control register) are transmitted for the CPU in the
cyclic range of PROFIBUS DP.
The contents of the status register can be used in the AS for generation of a field station-global group alarm.
In the case of applications without Stahl CPU redundancy, the function on the control register is deactivated
by parameter ´CPU redundant = No´ (default setting).
Using GSE V2.xx and V3.XX this data is included in the CPM Module descriptor.
Using GSE V4.xx or V5.xx with the 9442 CPU the optional module descriptor ´CPU status / control registers´
can be projected on any slot optionally if necessary. The slot address of the following IO-Modules are moved
in this case.
Maximum of 15 IO-M status / control registers are configurable, as far as no cyclical data length
limits are violated.
Hint: If the status / control registers is projected as the last module the after the real plugged IO-Module, the
slot addresses of the real plugged IO-Modules remain unchanged.
Control register CPU
If using redundant CPUs according Stahl specification, the control register serves to control the operating
states of the two redundant CPUs. The same value has to be transmitted to both CPUs. It is strongly
recommended to use the values 1 and 2 only for control of the redundancy switching.
In the case of applications with CPU redundancy according PNO Spec. the control register is not used.
7
0
Bit no.
0
0
0
0
0
0
x
x
0 = maintain status, outputs in safety position
1 = enable left CPU
2 = enable right CPU
3 = maintain status, outputs active
Reserved
Status register CPU
The status register contains information on both possible CPUs (left and right).
In the case of operation without CPU redundancy, only the status of the left CPU must be evaluated.
The status register can be used to read back the current status of the two CPUs for checking by the AS:
7
0
Bit No.
0
1
1
0
1
1
0
0
0 = no CPU is primary (active)
1 = left CPU is primary
2 = right CPU is primary
Status left CPU
Status right CPU
