AN543
Rev. 0.9
3
Two-wire bus mode uses the SCL and SDA pins for signaling. A transaction begins with the START condition,
which occurs when SDA falls while SCL is high. Next, the system controller drives an 8-bit control word serially on
SDA, which is captured by the device on rising edges of SCL. The control word consists of a seven-bit device
address followed by a read/write bit (read = 1, write = 0). The device acknowledges the control word by driving
SDA low on the next falling edge of SCL.
For write operations, the system controller next sends a data byte on SDA, which is captured by the device on
rising edges of SCL. The device acknowledges each data byte by driving SDA low for one cycle on the next falling
edge of SCL. For each write transaction, the first byte is a command and the following bytes are arguments.
For read operations, after the device has acknowledged the control byte, it will drive an eight-bit data byte on SDA,
changing the state of SDA on the falling edges of SCL. The system controller acknowledges each data byte by
driving SDA low for one cycle on the next falling edge of SCL. If a data byte is not acknowledged by the system
controller, the transaction will end. For each read transaction, the first byte is the status byte and the following bytes
are the response data from the receiver.
A 2-wire transaction ends with the STOP condition, which occurs when SDA rises while SCL is high.
5. Powerup and Powerdown
There are two procedures for powering up a receiver to move it from powerdown mode to the powerup mode. The
first is a powerup from internal receiver memory. The second is a powerup from a firmware component patch that is
stored in system controller memory. Patches can be applied to a firmware component by the system controller via
a download mechanism to address field issues, errata, or adjust device behavior. Patches are encrypted and
unique to a particular device firmware version, cannot be generated by customers, and can be used to replace a
portion of the component (to address errata, for example) or to download an entirely new component. The user
must verify that the device contains the correct base firmware to support the patch as described later in this
section.
It has been noted that some crystals require greater startup current and settling times than others. The procedure
below is meant to apply to a wide variety of such crystals, providing maximum current and 40 ms for crystal
oscillation to stabilize. If there are still difficulties with POWER-UP that may be related to your choice of crystal,
please refer to the settings and hardware options in “AN750: Si475x 4 MHz Crystal Compatibility Power-Up
Procedure”.
