SenTech STC-GE33OX Скачать руководство пользователя страница 27

Страница: 27 / 76

No.11S098-03

STC-GE33OX/GEC33OX
Users guide Rev. 1.03

3.3.2 Connection between user configurable FPGA (XILINX) and DDR2

(Note) Signal directions indicated as inputs and outputs

are referencing to the user FPGA. “Input” means a

signal from the DDR2 to the user FPGA

and “output” means from the user FPGA to DDR2.

Please sets Float, Pull-up or Pull-down for unused input and I/O signal of the user configurable FPGA.
Please sets Pull-up or Pull-down, or sets [H] or [L] with RTL code, for unused output signal of the user
configurable FPGA.

(Table-5) Connection between user configurable FPGA (XILINX) and DDR2

Signal Name

Direction Discription

Pin No. of User FPGA

1 DDR_A0

output

Address0

2 DDR_A1

output

Address1

3 DDR_A2

output

Address2

4 DDR_A3

output

Address3

5 DDR_A4

output

Address4

6 DDR_A5

output

Address5

7 DDR_A6

output

Address6

8 DDR_A7

output

Address7

9 DDR_A8

output

Address8

10 DDR_A9

output

Address9

11 DDR_A10

output

Address10

12 DDR_A11

output

Address11

13 DDR_A12

output

Address12

14 DDR_A13

Not use

15 DDR_A14

Not use

16 DDR_A15

Not use

17 DDR_BA0

output

Bank address0

18 DDR_BA1

output

Bank address1

19 DDR_BA2

Not use

20 DDR_D0

I/O

Data0

21 DDR_D1

I/O

Data1

22 DDR_D2

I/O

Data2

23 DDR_D3

I/O

Data3

24 DDR_D4

I/O

Data4

25 DDR_D5

I/O

Data5

26 DDR_D6

I/O

Data6

27 DDR_D7

I/O

Data7

28 DDR_D8

I/O

Data8

29 DDR_D9

I/O

Data9

30 DDR_D10

I/O

Data10

31 DDR_D11

I/O

Data11

32 DDR_D12

I/O

Data12

33 DDR_D13

I/O

Data13

34 DDR_D14

I/O

Data14

35 DDR_D15

I/O

Data15

36 DDR_RAS#

output

Command inputs

37 DDR_CAS#

output

Command inputs

38 DDR_WE#

input

Command inputs

39 DDR_CKE

output

Clock enable

40 DDR_CK

output

Clock

41 DDR_CK#

output

Clock

42 DDR_LDQS

I/O

Data strobe for lower byte

43 DDR_LDQS#

I/O

Data strobe for lower byte

44 DDR_UDQS

I/O

Data strobe for upper byte

45 DDR_UDQS#

I/O

Data strobe for upper byte

46 DDR_ODT

output

On-die termination

47 DDR_LDM

output

Input data mask for lower byte U1

48 DDR_UDM

output

Input data mask for upper byte R6

Содержание STC-GE33OX

Страница 1: ...No 11S098 03 1 STC GE33OX GEC33OX Users guide Rev 1 03 Sentech Power Plus VGA Color Monochrome CCD GigE Vision Camera STC GE33OX STC GEC33OX Users guide Sentech Co Ltd ...

Страница 2: ... 1 01 2012 01 31 Update Change add and delete the camera control commands Add the strobeSignal for the output signal Change the GenICam command Camera command reference table 1 02 2012 04 12 Update Update the GenICam command Camera command reference table 1 03 2017 04 17 Update Address TEL FAX number for relocation ...

Страница 3: ...rmation between the devices 25 3 3 1 Connection between the user configurable FPGA XILINX and the Sentech FPGA 25 3 3 2 Connection between user configurable FPGA XILINX and DDR2 27 3 3 3 Connection between the user configurable FPGA XILINX and the EEPROM 28 3 4 Development guideline 29 3 4 1 Module and constraints files 29 3 4 2 Important design cautions 29 3 4 3 Notice for use DDR2 memory 30 3 4 ...

Страница 4: ...mode The trigger input while the image is out 41 5 4 1 Timing 41 5 4 2 Exposure timing with the positive polarity trigger signal 42 5 4 3 Exposure timing with the negative polarity trigger signal 42 5 5 H reset mode 43 6 The communication protocol specifications 44 6 1 The communication method 44 6 2 The communication settings 44 6 3 The communication format 45 6 4 The camera control commands 47 6...

Страница 5: ...No 11S098 03 5 STC GE33OX GEC33OX Users guide Rev 1 03 This document is the connectivity and operation users guide for STC GE33OX GEC33OX ...

Страница 6: ...FF Green LED Blinking 100Mb transferring NIC HUB or LAN cable is not support 1Gb Please use 1Gb supported NIC HUB and LAN cable Please check the NIC and HUB setting is 1Gb transferring when use with 1Gb supported NIC and HUB When snapping of the CAT5e cable possibility to change the transferring speed from 1Gb to 100Mb Please change the CAT5e cable Pin No Signal name 1 TA 2 TA 3 TB 4 TC 5 TC 6 TB ...

Страница 7: ...ctor while the power input though PoE No Signal type IO direction Spec Initial signal 1 POWER IN GND GND 2 POWER IN 10 8 to 26 4Vdc 3 OUT0_AUX_OP OUT Opt Isolated FrametriggerWait out 4 OUT1_AUX_OP OUT Opt Isolated ExposureActive out 5 OUT2_AUX_OP OUT Opt Isolated Open 6 OUT3_AUX_OP OUT Opt Isolated Open 7 OUT4_AUX_OP OUT Opt Isolated Open 8 IN0_AUX_OP IN Opt Isolated TRG In 9 IN1_AUX_OP IN Opt Is...

Страница 8: ...tarts while the image output by next trigger signal please change the camera setting Device code 00H Command 13H to accept the trigger signal while the image output The noise appears on the image when start exposure while the image output In this case please change the H reset for the exposure start mode Device code 00H Command 12H to change the exposure start point to next HD timing B UserOutput ...

Страница 9: ...No 11S098 03 9 STC GE33OX GEC33OX Users guide Rev 1 03 1 3 DC IRIS lens connector Connector M1951 EMUDEN or equivalent Pin assignment 1 2 3 4 Pin No Signal name 1 DAMP 2 DAMP 3 DRIVE 4 DRIVE ...

Страница 10: ...ircuits CAMERA Response time 11 ns 11 ns 11 ns 11 ns Tf 520 ns 545 ns 584 ns 689 ns Ts 100 ns 100 ns 100 ns 100 ns Tr 3 0 us 3 0 us 2 8 us 2 5 us Td 24 V 12 V 5 0 V 3 3 V IO_VCC 10 90 Td Ts Tr Tf USER INPUT INPUT OPTO ISOLATOR SHARP PC400J00000F IO_VCC CAM_VCC If INPUT USER_INPUT Maximum consumption of If is 6 mA ...

Страница 11: ...3OX Users guide Rev 1 03 Example circuit for the input signal USER_INPUT OPTO ISOLATOR SHARP PC400J00000F IO_VCC CAMERA CAM_VCC IO_GND If INPUT OPTO ISOLATOR SHARP PC400J00000F IO_VCC CAMERA CAM_VCC IO_GND If INPUT IO_VCC USER_INPUT ...

Страница 12: ...ircuits OPTO ISOLATOR SHARP PC354NJ0000F IO_VCC USER_OUTPUT OUTPUT IO_GND 10k Ohm CAMERA Ts Td 10 90 Tr Tf OUTPUT USER_OUTPUT Response time 10 9 us 6 9 us 3 8 us 3 1 us Tf 2 8 us 2 8 us 2 2 us 2 2 us Ts 31 0 us 42 3 us 60 2 us 67 5 us Tr 28 4 us 35 2 us 30 4 us 29 6 us Td 24 V 12 V 5 0 V 3 3 V IO_VCC ...

Страница 13: ...le FPGA XILINX information 3 1 1 Device information The manufacturer names and item numbers of the user configurable FPGA and the peripheral devices are listed in the table 1 3 1 2 User program examples Implementation of proprietary algorithm Image processing and conversion Image storage Image analysis Pattern comparison and others Device Part number Size Manufacture FPGA XC3SD1800A Package CSG484...

Страница 14: ... E I F User configuration FPGA XILINX Camera Gigabit Ethernet port DDR2 Memory 32MB Image data UART User configuration FPGA XILINX area Configuration SPI BUS EEPROM 512Kbit Configuration ROM 8Mbit 12bit image data Clock FVAL LVAL 25MHz Power IO connector JTAG connector 3 inputs 5 outputs JTAG TCK TMS TDI TDO I O JTAG Fig 1 Block diagram ...

Страница 15: ...a is sent into Sentech FPGA the image data can be routed to User Configurable FPGA Three different extraction points are provided in Sentech FPGA for this purpose Please see Section 3 2 2 1 2 2 for more details 4 This data is further processed by the program you create in User Configurable FPGA 5 Now the data should be returned to Sentech FPGA In this process again three different points are provi...

Страница 16: ...he user FPGA processed and inserted back to Sentech FPGA 1 Image data flow block diagram CCD CDS AD Sentech FPGA User configurable FPGA XILINX DIN0 11 White Balance Gamma Color Interpolation The image data from Sentech FPGA to user configurable FPGA A B C Sentech FPGA User configurable FPGA XILINX DOUT0 11 White Balance Gamma Color Interpolation The image data from user configurable FPGA to Sentch...

Страница 17: ... After processing the 12 bit image data in the user FPGA the data is inserted back to the Sentech FPGA as DOUT11 0 at any points listed below These points A B and C are again indicated in fig 2 Image data flow block diagram A For the color camera A Before the white balance the gamma and color interpolation processing B Before the gamma and the color interpolation processing C Before the color inte...

Страница 18: ...rable FPGA at Process after User FPGA Sentech FPGA Selection Color camera Monochrome camera CCD data CCD raw data CCD raw data White balance processed data White balance processed image data CCD raw data White balance and White balance processed and Gamma processed image data gamma processed data gamma processed image data Image data from Sentech FPGA Selection Color camera Monochrome camera No pr...

Страница 19: ...TC GE33OX GEC33OX Users guide Rev 1 03 B By changing the register value through the UART Also please see section 6 The communication protocol specifications a Set the image data between FPGAs Device code 20H command C0H ...

Страница 20: ... when the user configurable FPGA has to configure with the uploaded configure data for the user configurable FPGA The user configurable FPGA does not work if select Disable at User FPGA Enable A By using Sentech GUI StCamGigEWare_OpDemo Also please see User configurable FPGA XILINX Sample Codes a Select OP Setting under Option in the menu b Select which image data sends from Sentech FPGA to User c...

Страница 21: ...formation 3 2 2 4 User I Os The camera provides total of eight I O points Three are designated as inputs and five as outputs Each I O point can be assigned or connected to any points in Sentech FPGA or User Configurable FPGA Please see table 4 and 2 I O circuits for more details Note Input s assignments in the Sentech FPGA are limited for the functions of Exposure out and Trigger ready 1 Conceptua...

Страница 22: ... above window Sentech FPGA send output signals to Output 1 and 2 of 12pin power IO connector User configurable FPGA send output signals to Output 3 4 and 5 of 12pin power IO connector B By changing the register value through the UART Also please see section 6 The communication protocol specifications a Set the output signal selection Device code 20H command C1H Select the output signal from the Se...

Страница 23: ...r configurable FPGA Through this communication channel you can change register values in User configurable FPGA 1 Please change the UART port from the UART0 to the UART1 1 Please setup UART port as following Baud rate 115 200bps Data bit 8bit Parity None Stop bit 1bit Flow control None Fig 4 UART diagram Sentech FPGA User configurable FPGA XILINX Ethernet connector USER_ TXD_PC USER_ RXD_PC ...

Страница 24: ...ay equivalent to the process time in the user FPGA on LVALIN and FVALIN 3 As the data is sent back to the Sentech FPGA DIN image data LVALIN and FVALIN must be activated at the rising edges of CLKIN CLKIN 36 81MHz CLKIN DIN 11 0 LVALIN FVALIN D0 D1 D2 D3 D4 Dx CLKIN DOUT 11 0 LVALOUT FVALOUT D0 D1 D2 D3 D4 Dx Number of clock for image processing Number of clock for image processing Number of pixel...

Страница 25: ...3 FVALIN input FVAL C13 14 LVALIN input LVAL C15 15 DOUT0 output Image Data bit0 B13 16 DOUT1 output Image Data bit1 B15 17 DOUT2 output Image Data bit2 A16 18 DOUT3 output Image Data bit3 A9 19 DOUT4 output Image Data bit4 A17 20 DOUT5 output Image Data bit5 B9 21 DOUT6 output Image Data bit6 C4 22 DOUT7 output Image Data bit7 C6 23 DOUT8 output Image Data bit8 C7 24 DOUT9 output Image Data bit9 ...

Страница 26: ...rred between the Sentech FPGA and the user FPGA is 12 bit data The MSB Most Significant Bit is bit 11 and the LSB Least Significant Bit is bit 0 DIN0 11 is the data from the Sentech FPGA to the user PGA and DOUT0 11 is the data from the user PGA to the Sentech FPGA Please sets Float Pull up or Pull down for unused input signal of the user configurable FPGA Please sets Pull up or Pull down or sets ...

Страница 27: ...output Address10 V4 12 DDR_A11 output Address11 W2 13 DDR_A12 output Address12 W3 14 DDR_A13 Not use F1 15 DDR_A14 Not use F5 16 DDR_A15 Not use F4 17 DDR_BA0 output Bank address0 H5 18 DDR_BA1 output Bank address1 H1 19 DDR_BA2 Not use H2 20 DDR_D0 I O Data0 Y1 21 DDR_D1 I O Data1 W1 22 DDR_D2 I O Data2 R3 23 DDR_D3 I O Data3 T4 24 DDR_D4 I O Data4 T1 25 DDR_D5 I O Data5 R5 26 DDR_D6 I O Data6 T6...

Страница 28: ...or unused input signal of the user configurable FPGA Please sets Pull up or Pull down or sets H or L with RTL code for unused output signal of the user configurable FPGA No Signal Name Direction Discription Pin No of User FPGA 1 ROM_512KBIT_CLK output Serial Clock for ROM U20 2 ROM_512KBIT_nS output Chip Select for ROM T17 3 ROM_512KBIT_DATA output Serial Data input for ROM T20 4 ROM_512KBIT_Q inp...

Страница 29: ...LKIN 2 In the same manner the signal timings of the image data LVAL and FVAL after image processing must be latched at the rising edges of the clock pulse symbol CLKIN 3 When a selector is used in the process as shown as an example in the drawing the signal timings of the image data LVAL and FVAL must be latched at the rising edges of the clock pulse symbol CLKIN 4 The image data LVAL and FVAL mus...

Страница 30: ...o use DDR2 memory Setting Item Setting Value Burst Length 4 Burst Type Sequential Output Driver Strength Fullstrength RTT nominal ODT 75Ohm DQS Enable Enable USE DCM check Class for Address and Control Class II Class for Data Class II Debug Signal for Memory Controller Disable System Clock Signal Ended 105 line of mig_dcm_ddr2_infrastructure_top v generate if CLK_TYPE DIFFERENTIAL begin DIFF_ENDED...

Страница 31: ... can use for the security key Please check the XILINX application note WP266 3 4 6 Schematics of the user configurable FPGA XILINX Please check Schematics of user configurable FPGA XILINX Image processing 1 Image processing 2 Image processing 3 User configurable FPGA The image data DIN LVALIN FVALIN from the Sentech FPGA is Flip Flop output with the rising edge of CLKIN after input image data The ...

Страница 32: ...g 1 CLK 27 1605 nseconds 4 1 1 Color Bayer order This information is only for STC GEC33OX R1 Gr1 R2 Gb1 Gb2 B1 Gr2 B2 Video out Line 1 Video out Line 2 LVAL R3 Gb3 Gr3 B3 132 CLK 648 CLK Video out LVAL DVAL Horizontal blanking 780 CLK One horizontal 1H 648 CLK 132 CLK 132 CLK Video output 132 CLK 94 CLK 38 CLK FVAL ...

Страница 33: ...E33OX GEC33OX Users guide Rev 1 03 4 2 The vertical timing 4 2 1 Full scanning 1 H 21 1852 µseconds 89 910172 Hz 31H 494H Video out FVAL Vertical blanking 525H One vertical 1V 494H 31H 31H Video output 1 2 493 494 31H LVAL ...

Страница 34: ...xposure time V1 V2 V3 SUB FVAL LVAL Number of the effective lines Y High speed transfer X a High speed transfer f g X Y Blanking Front BLK_F Number of the effective lines Y Total number of the line at 1 frame TOTAL_LINE Blanking Back BLK_B CCD effective lines Blanking Front Effective lines Optical black Dummy bit Blanking Back Optical black ...

Страница 35: ...ing image STC GE33OX Monochrome Pixeln of Data The transferring pixel n The order number STC GEC33OX Color Pixelmn of Data The transferring pixel m The line number n The order number Pixel1 of Data Pixel2 of Data Pixel11 of Data Pixe12 of Data Pixel21 of Data Pixel22 of Data ...

Страница 36: ...No 11S098 03 36 STC GE33OX GEC33OX Users guide Rev 1 03 5 Camera function modes 5 1 Normal mode E x p o s u r e t i m e I n t e r n a l V D C C D e x p o s u r e V i d e o o u t ...

Страница 37: ...er pulse Therefore In the case of the exposure positive polarity is selected the exposure periods are the high states of the trigger pulse 5 2 1 Timing Note 1 The video output is going to be V reset by the next internal HD signal immediate after the exposure is finished Note 2 The exposure time sets by the pulse width of the trigger signal Exposure time Max 1H Internal VD CCD exposure Trigger sign...

Страница 38: ...larity trigger signal Note 1 The trigger signal is removed by the filtering if the pulse width of the input trigger signal is less than 30 CLK Please input the trigger signal has more then 31 CLK pulse width Note 2 The exposure is going to start 75 CLK after the rising edge of the trigger signal T1 SUB SG 127 CLK Input Trigger signal Exposure time Exposure time T1 T1 127 CLK T1 30 CLK Filtering No...

Страница 39: ...pulse Exposure duration time is preset by the DIP Switch settings 5 3 1 Timing Note 1 The video output is going to be V reset by the next internal HD signal immediate after the exposure is finished Note 2 The exposure time sets by the preset electronic shutter speed Exposure time Max 1H Internal VD CCD exposure Trigger signal Rising edge Video out Note 1 Note 2 FVAL ...

Страница 40: ...ve polarity trigger signal Note 1 The trigger signal is removed by the filtering if the pulse width of the input trigger signal is less than 30 CLK Please input the trigger signal has more then 31 CLK pulse width Note 2 The exposure is going to start 75 CLK after the rising edge of the trigger signal Input Trigger signal Exposure time T1 SUB SG Exposure time T1 Preset exposure time Filtering Note ...

Страница 41: ...gnal mask with the communication when the trigger signal input is required while the image is out It is necessary to set the H reset at the exposure start mode for do not generate the additional noise on the image 5 4 1 Timing Note 1 The video output is going to be V reset by the next internal HD signal immediate after the exposure is finished Note 2 The exposure time sets by the preset electronic...

Страница 42: ...ve polarity trigger signal Note 1 The trigger signal is removed by the filtering if the pulse width of the input trigger signal is less than 30 CLK Please input the trigger signal has more then 31 CLK pulse width Note 2 The exposure is going to start 75 CLK after the rising edge of the trigger signal Input Trigger signal Exposure time T1 SUB SG Exposure time T1 Preset exposure time Filtering Note ...

Страница 43: ...ulse to sweep the charges during the horizontal blanking to prevent from getting horizontal noises The image is getting the horizontal noises caused by generates the SUB pulse during the video out in normal mode which is this mode is OFF The maximum delay to start exposure from the trigger input is 1H Next HD Video out SUB pulse Internal HD CCD exposure Trigger signal Rising edge Noise Normal SUB ...

Страница 44: ...al devises like PC control the camera functions Please use StCamGigEWare or StGigECtrl communication software or use following the communication protocol to communicate to the camera 6 1 The communication method UART RS232C Binary communication 6 2 The communication settings Settings Baud rate 115 200bps Data bit 8bit Parity None Stop bit 1bit Flow control None ...

Страница 45: ...s 1 byte when send read command The data of the EEPROM is replaced by sent data when sent write command The camera sends the receiving coce as 01H to the PC after the data of the EEPROM is replaced Sets or gets the value is as 02H always Sets or gets 1 when send write command Sets 0 when access to the command register of the camera The data of the command register is replaced by the sent data when...

Страница 46: ... GEC33OX Users guide Rev 1 03 D Example command Send the read command to read the 00H address data of the register 02 00 00 01 00 03 SOF Device code Read Register Command code Data length Data EOF The return command 02 01 00 03 ...

Страница 47: ...bit D 23 16 53H Read Write x The trigger delay time useconds Decimal 8bit D 7 0 54H Read Write x The strobe signal delay time useconds Integer 24bit D 7 0 55H Read Write x The strobe signal delay time useconds Integer 24bit D 15 8 56H Read Write x The strobe signal delay time useconds Integer 24bit D 23 16 57H Read Write x The strobe signal delay time useconds Decimal 8bit D 7 0 58H Read Write x F...

Страница 48: ...area 16bit D 7 0 37H Read Write x Vertical_4 position for the ALC weight area 16bit D 15 8 38H Read Write x Horizontal_1 position for the ALC weight area 16bit D 7 0 39H Read Write x Horizontal_1 position for the ALC weight area 16bit D 15 8 3AH Read Write x Horizontal_2 position for the ALC weight area 16bit D 7 0 3BH Read Write x Horizontal_2 position for the ALC weight area 16bit D 15 8 3CH Rea...

Страница 49: ...izontal_1 position for the white balance area 16bit D 15 8 5EH Read Write x Horizontal_2 position for the white balance area 16bit D 7 0 5FH Read Write x Horizontal_2 position for the white balance area 16bit D 15 8 60H Read Write x Camera mode1 8bit D 7 0 61 to 7FH Reserved 80H Read Write x Push set white balance Red gain 8bit D 7 0 81H Read Write x Push set white balance Gr gain 8bit D 7 0 82H R...

Страница 50: ...0 No function Sets always as 111 as manual 12H MOD3 7 0 D7 to D6 No function Sets always as 00 D5 Trigger signal type 0 Software trigger 1 Hardware triger D4 to D3 Exposure start mode 00 Normal 10 to 11 H reset D2 to D0 No function Sets always as 000 Sets the camera function mode D 7 0 Note 1 Function mode is enable when the Continuous Trigger mode MOD1 D7 is Note 2 No video output without the tri...

Страница 51: ...ignal with Generate command software trigger SOFTRIG D0 Note 3 When use User configurable FPGA generates trigger Please generate the trigger signal has more than 200 useconds pulse duration in the user configurable FPGA Command descriptions The camera function mode 4 Initial data 60H Software trigger setting Initial data 00H Sets the camera function mode D 7 0 1 ON Invalid the trigger signal while...

Страница 52: ...H GOFS 7 0 Command descriptions The exposure time useconds of the electronic shutter CDS gain Initial data PGA 7 0 0 data range 0 to 255 Initial data EXPTM 23 0 0 data range 0 to 16 777 215 Sets the exposure time for electronic shutter Exposure time EXPTM 23 0 useconds When sets as 0 the electronic shutter is OFF The gain offset The value of the address 32H Sets the CDS gain programable gain CDS g...

Страница 53: ... 0 to 4 095 Initial data DELAY_F 23 0 0 data range 0 to 99 The delay time usecond decimal for the trigger signal Sets the delay time that is from the trigger signal input to start exposure as usecond Delay time for the trigger signal DELAY_I 23 0 DELAY_F 7 0 useconds The digital gain Initial data DGB 7 0 The factory adjusted value Video level Input video level CLAMP level x 1 DGB 7 0 128 CLAMP Lev...

Страница 54: ...range Max frame rate for full resolution D 7 0 The polarity of the output signal for 4 pin of the power IO connector The polarity of the output signal for 3 pin of the power IO connector The polarity of the output signal for 6 pin of the power IO connector The polarity of the output signal for 5 pin of the power IO connector The polarity of the output signal for 7 pin of the power IO connector Com...

Страница 55: ...bit gradation 0A to 7FH No function Prohibited setting Do not set these values 80H E2P 7 0 D 7 0 D7 to D1 No function Sets always as 0000000 D0 Write control to the EEPROM 0 Prohibited 1 Accept Sets the test pattern output form the camera D 7 0 Test pattern selection Initial data TESTP 7 0 00H EEPROM control Initial data E2P 7 0 00H Command descriptions Image effect selection Initial data EFFCT 7 ...

Страница 56: ...Sets the output signal from the power IO connector Sets the active time for the strobe signal as usecond Active time for the strobe signal STROBEON_I 23 0 STROBEON_F 7 0 useconds The strobe signal active time usecond integer Initial data STROBEDELAY_I 23 0 0 data range 0 to 2 000 000 Sets the active time for the strobe signal as usecond Active time for the strobe signal STROBEON_I 23 0 STROBEON_F ...

Страница 57: ...ith 4 TriggerInternal signal after mask and delay process Prohibited setting Do not set this value Note UserOutput signal is enable when UserOutput signal select at Sets the status of the UserOutput signal D 7 0 UserOutput signal for 7pin of the power IO UserOutput signal for 6pin of the power IO UserOutput signal for 5pin of the power IO UserOutput signal for 4pin of the power IO UserOutput signa...

Страница 58: ...unction Command descriptions Output signal for 7 pin of the power IO connector The output signal selection for the power IO connector Initial data OUTSEL2 7 0 00H Sets the output signal from the power IO connector D 7 0 4 TriggerInternal signal after mask and delay process Prohibited setting Do not set this value Note When select UserOutput signal sets the status of the signal with UserOutput sign...

Страница 59: ...utter for auto shutte as usecond JTAG for the user configurable FPGA Initial data 00H Sets the JTAG connection ON OFF for the user configurable FPGA D 7 0 The user configurable FPGA enable Initial data 00H Sets the user configurable FPGA is Enable Disable when statrt up the camera D 7 0 User configurable FPGA D 7 0 The lower limit of the electronic shutter for auto shutter Initial data 0 data rang...

Страница 60: ... D0 Weight for ALC weight area 7 1 Range 0 to 15 D 7 0 Please set the ALC weight area with 30H to 3FH D 7 0 Please set the ALC weight area with 30H to 3FH Weight4 for ALC Initial data 11H Sets the weight for ALC weight area 7 and 8 Command descriptions Weight3 for ALC Initial data 1AH Sets the weight for ALC weight area 5 and 6 Sets the weight for ALC weight area 3 and 4 D 7 0 Weight2 for ALC Init...

Страница 61: ...ght area Command descriptions Target brightness for ALC Initial data 128 data range 0 to 255 Sets the target brightness for the ALC function AGC auto shutter or iris lens auto control Weight5 for ALC Initial data 01H Sets the weight for ALC weight area 9 D 7 0 Please set the ALC weight area with 30H to 3FH Initial data 32 data range 0 to 493 Initial data 169 data range 0 to 493 ALC peak average In...

Страница 62: ...0 to 647 Horizontal_2 position for the ALC weight area Initial data 252 data range 0 to 647 Sets the horizontal 2 position for ALC weight area Horizontal_3 position for the ALC weight area Sets the horizontal 4 position for ALC weight area Initial data 396 data range 0 to 647 Sets the horizontal 3 position for ALC weight area Horizontal_4 position for the ALC weight area Initial data 612 data rang...

Страница 63: ...l data 0 data range 0 to 255 Sets the Red gain for the preset_1 white balance Sets the white balance mode for the color camera D 7 0 When use the push to set white balance set the white balance mode as Push to set white balance then change 0 to 1 for Push to set white balance operation Sets the Gr gain for the preset_1 white balance Sets the Blue gain for the preset_1 white balance Preset_1 white ...

Страница 64: ...e Red gain for the preset_2 white balance Sets the Gb gain for the preset_1 white balance Preset_1 white balance Gb gain Initial data 0 data range 0 to 255 Gb of the camera output image data CCD_Gb CLAMP Level x 1 GainGb1 7 0 64 CLAMP Level Preset_2 white balance Gr gain Initial data 0 data range 0 to 255 Preset_2 white balance Red gain Initial data 0 data range 0 to 255 CCD_R CLAMP Level x 1 Gain...

Страница 65: ...the pixel is greater than this value Command descriptions Preset_3 white balance Blue gain Initial data 0 data range 0 to 255 Preset_3 white balance Gb gain Initial data 0 data range 0 to 255 Bright level threshold for auto white balance process Initial data 3 072 data range 0 to 4 095 Sets the Gb gain for the preset_3 white balance Sets the Blue gain for the preset_3 white balance Preset_3 white ...

Страница 66: ... Height for AOI Sets the height which is the vertical size of the image for the AOI Initial data 0 data range 2 Y_offset Height 494 Initial data 0 data range 8 X_offset Width 648 Width for AOI Initial data 648 data range 8 X_offset Width 648 Sets the width which is the horizontal size of the image for the AOI Vertical_1 position for the white balance area Initial data 0 data range 0 to 493 Sets th...

Страница 67: ... the camera output image data CCD_R CLAMP Level x 1 GainRP 7 0 64 CLAMP Level CLAMP Level Clamp level The calculated value of 38H Push to set white balance Gr gain Initial data 0 data range 0 to 255 Sets the Gr gain for the Push to set white balance Gr of the camera output image data CCD_Gr CLAMP Level x 1 GainGrP 7 0 64 CLAMP Level CLAMP Level Clamp level The calculated value of 38H Push to set w...

Страница 68: ...tial data 01H Sets the iris lens manual adjustment operation D 7 0 Image data between FPGAs Initial data 00H D 7 0 Image process after the image data from the user configurable FPGA 00 No process No data from use FPGA No image data from the use configurable FPGA 01 White balance gamma and color interpolation 10 Gamma and color interpolation 11 No function Note White balance and color interpolation...

Страница 69: ...A 1 Output signal from the user configurable FPGA Output signal for 6 pin Out3 of the power IO connector 1 Output signal from the user configurable FPGA Output signal for 5 pin Out2 of the power IO connector 0 Output signal from Sentech FPGA 0 Output signal from Sentech FPGA 1 Output signal from the user configurable FPGA 0 Output signal from Sentech FPGA 1 Output signal from the user configurable...

Страница 70: ...receiving code after write EEPROM 01H OK 17H EEPROM write error 4 80H 0 is changed to 0 automatically after write EEPROM Note 1 DO NOT saves to the EEPROM when 80H 0 is 0 Note 2 When save the multiple sequence command to the EEPROM all data save to the EEPROM by one operation from 1 to 4 Example of the multiple sequence command 10H 11H 12H and 13H or 22H 23H and 24H Note 3 When save the multiple c...

Страница 71: ...000 16H 0 Generate command software trigger TriggerSoftwareSource 000000 16H 6 7 Software trigger source selection TriggerMode 000000 11H 3 Function mode LineSource0 000000 F0H 0 3 Output signal for 3 pin of the power IO connector LineSource1 000000 F0H 4 7 Output signal for 4 pin of the power IO connector LineSource2 000000 F8H 0 3 Output signal for 5 pin of the power IO connector LineSource3 000...

Страница 72: ...l s polarity for 4 pin of the power IO connector LineInverter2 000000 5DH 2 Output signal s polarity for 5 pin of the power IO connector LineInverter3 000000 5DH 3 Output signal s polarity for 6 pin of the power IO connector LineInverter4 000000 5DH 4 Output signal s polarity for 7 pin of the power IO connector StrobeSignalOnTime 000000 90 93H Strobe signal active time StrobeSignalDelay 000000 54 ...

Страница 73: ...alance Blue gain BalanceRatio_Gb_Preset3 100000 4CH Preset3 white balance Gb gain BalanceRatio_R_Once 100000 80H Push to set white balance Red gain BalanceRatio_Gr_Once 100000 81H Push to set white balance Gr gain BalanceRatio_B_Once 100000 82H Push to set white balance Blue gain BalanceRatio_Gb_Once 100000 83H Push to set white balance Gb gain GainAuto 100000 20H 3 AGC GainRaw 000000 30H CDS gain...

Страница 74: ...or the ALC weight area ALCWindowV4 100000 36 37H Vertical4 position for the ALC weight area ALCWindowH1 100000 38 39H Horizontal1 position for the ALC weight area ALCWindowH2 100000 3A 3BH Horizontal2 position for the ALC weight area ALCWindowH3 100000 3C 3DH Horizontal3 position for the ALC weight area ALCWindowH4 100000 3E 3FH Horizontal4 position for the ALC weight area WB_WindowH1 100000 58 59...

Страница 75: ... size Please use GenICam command name command when change these values like below sample code In the case to change the Width BOOL SetWidth PvDevice pDevice PvInt64 lValue PvGenInteger lGenInteger dynamic_cast PvGenInteger pDevice GetGenParameters Get Width PvResult lResult lGenInteger SetValue lValue return lResult IsOK ...

Страница 76: ...1S098 03 76 STC GE33OX GEC33OX Users guide Rev 1 03 9F Ebina Prime Tower 9 50 Chuo 2 Chome Ebina city Kanagawa 243 0432 JAPAN Sentech Co Ltd TEL 81 46 236 6660 FAX 81 46 236 6661 URL http www sentech co jp ...

Результаты поиска

Содержание STC-GE33OX

Отзывы:

Похожие инструкции для STC-GE33OX

Бренды по названию

Популярные бренды

SenTech STC-GE33OX, Руководство пользователя

Результаты поиска

Содержание STC-GE33OX

Отзывы:

Похожие инструкции для STC-GE33OX

Бренды по названию

Популярные бренды