No.11S098-03
25
STC-GE33OX/GEC33OX
Users guide Rev. 1.03
3.3 Connection information between the devices
It is not necessary to consider these data pin assignments if use the pin assignment and the timing constraints file
(power_plus_000.ucf).
3.3.1 Connection between the user configurable FPGA (XILINX) and the Sentech FPGA
(Table-4) Connection between the user configurable FPGA (XILINX) and the Sentech FPGA
No
Signal Name
Direction Discription
Pin No. of User FPGA
1 DIN0
input
Image Data bit0
B6
2 DIN1
input
Image Data bit1
A6
3 DIN2
input
Image Data bit2
A7
4 DIN3
input
Image Data bit3
A5
5 DIN4
input
Image Data bit4
B3
6 DIN5
input
Image Data bit5
B4
7 DIN6
input
Image Data bit6
A3
8 DIN7
input
Image Data bit7
A4
9 DIN8
input
Image Data bit8
A8
10 DIN9
input
Image Data bit9
B11
11 DIN10
input
Image Data bit10 B8
12 DIN11
input
Image Data bit11 A11
13 FVALIN
input
FVAL
C13
14 LVALIN
input
LVAL
C15
15 DOUT0
output
Image Data bit0
B13
16 DOUT1
output
Image Data bit1
B15
17 DOUT2
output
Image Data bit2
A16
18 DOUT3
output
Image Data bit3
A9
19 DOUT4
output
Image Data bit4
A17
20 DOUT5
output
Image Data bit5
B9
21 DOUT6
output
Image Data bit6
C4
22 DOUT7
output
Image Data bit7
C6
23 DOUT8
output
Image Data bit8
C7
24 DOUT9
output
Image Data bit9
C8
25 DOUT10
output
Image Data bit10 C9
26 DOUT11
output
Image Data bit11 C12
27 FVALOUT
output
FVAL
A13
28 LVALOUT
output
LVAL
A14
29 CLKIN
input
CLK
F11
30 SYS_RST_N
input
SYSTEM_RESET AA12
31 USER_TXD_PC
input
UART_TX
E22
32 USER_RXD_PC
output
UART_RX
G22
34 USER_OUT_AUX0
output
USER_I/O
P22
35 USER_OUT_AUX1
output
USER_I/O
R22
36 USER_OUT_AUX2
output
USER_I/O
R20
37 USER_OUT_AUX3
output
USER_I/O
U22
38 USER_OUT_AUX4
output
USER_I/O
V20
39 USER_IN_AUX0
input
USER_I/O
W22
40 USER_IN_AUX1
input
USER_I/O
Y22
41 USER_IN_AUX2
input
USER_I/O
W19
42 ExposureActive
input
EXP_OUT
N17
43 FrameTriggerWait
input
TRG_RDY
N18
44 USER_TRG
output
TRG_OUT
D22
