No.11S098-03
30
STC-GE33OX/GEC33OX
Users guide Rev. 1.03
3.4.3 Notice for use DDR2 memory
DDR2 memory control IP core for the sample code was made by MIG3.3 (Core Generator) with the below
settings.
The generated file
(¥ipcore_dir¥mig_dcm_ddr2¥mig_dcm_ddr2¥user_design¥par¥mig_dcm_ddr2_infrastructure_tip.v) was
changed as below:
The timing constraints file, which is made by the IP core belong to ISE
(¥ipcore_dir¥mig_dcm_ddr2¥mig_dcm_ddr2¥user_design¥par¥mig_dcm_ddr2.ucf) is reflect to the
power_plus_000.ucf file.
The optional setting of the ISE was changed as below from the default setting, to use DDR2 memory.
Setting Item
Setting Value
Burst Length
4
Burst Type
Sequential
Output Driver Strength
Fullstrength
RTT(nominal)-ODT
75Ohm
DQS# Enable
Enable
USE DCM
check
Class for Address and Control
Class II
Class for Data
Class II
Debug Signal for Memory Controller
Disable
System Clock
Signal-Ended
105 line of mig_dcm_ddr2_infrastructure_top.v
/*
generate
if(`CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
IBUFGDS_LVDS_25 SYS_CLK_INST
(
.I (sys_clk),
.IB (sys_clkb),
.O (sys_clk_ibuf)
);
end else if(`CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
IBUFG SYS_CLK_INST
(
.I (sys_clk_in),
.O (sys_clk_ibuf)
);
end
endgenerate
*/
// CHANGE BY SENSOR TECHNOLOGY
assign sys_clk_ibuf = sys_clk_in;
Category
Property name Value
Synthesis OptionsKeep Hierarchy Soft
(Table-7) Setting of MIG3.3
(Table-8) Optional setting of ISE