USB CONTROLLER
S3C2500B
10-32
Table 10-20. USBEP2CSR Register Description (Continued)
Bit Number
Bit Name
MCU
USB
Description
[20]
Out mode,
Fifo FLUSH
(OFFLUSH)
R/W
C
This bit is valid only when endpoint 2 is set to OUT.
The MCU writes a “1” to flush the FIFO.
This bit can be set only when OORDY is set. The
packet due to be unloaded by the MCU will be
flushed.
[21]
Out mode,
SenD STALL
(OSDSTALL)
R/W
R
This bit is valid only when endpoint 2 is set to OUT.
The MCU writes a “1” to this bit to issue a STALL
handshake to the USB.
The MCU clears this bit to end the STALL condition
[22]
Out mode,
SenT STALL
(OSTSTALL)
R/C
S
This bit is valid only when endpoint 2 is set to OUT.
The USB sets this bit when an OUT token is ended
with a STALL handshake.
The USB issues a stall handshake to the host if it
sends more than MAXP data for the OUT token.
[23]
Out mode,
CLear data TOGgle
(OCLTOG)
R
S
This bit is valid only when endpoint 2 is set to OUT.
When the MCU writes a “1” to this bit, the data
toggle sequence bit is reset to DATA0.
[24]
In mode, IN packet
ReaDY (IINRDY)
R/S
C
This bit is valid only when endpoint 2 is set to IN.
The MCU sets this bit, after writing a packet of data
into the FIFO. The USB clears this bit once the
packet has been successfully sent to the host. An
interrupt is generated when the USB clears this bit,
so the MCU can load the next packet, While this bit
is set, the MCU will not be able to write to the FIFO.
If the SEND STALL bit is set by the MCU, this bit
can not be set.
[25]
In mode, fifo Not
EMPty (INEMP)
R
S
This bit is valid only when endpoint 2 is set to IN.
Indicate there is at least one packet of data in FIFO.
if USBEP2CSR[25:24] is
10 = 1 packet IN FIFO
11 = 2 packets of MAXP =< 1/2 FIFO or
1 packet of MAXP > FIFO size
[26]
In mode, UNDER
run (IUNDER)
R/C
S
This bit is valid only when endpoint 2 is set to IN
ISO.
The USB sets this bit when in ISO mode, an IN
token is received and the IINRDY bit is not set.
The USB sends a zero length data packet for such
conditions, and the next packet that is loaded into
the FIFO is flushed.
Содержание S3C2500B
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Страница 80: ...PRODUCT OVERVIEW S3C2500B 1 46 NOTES ...
Страница 296: ...MEMORY CONTROLLER S3C2500B 5 60 NOTES ...
Страница 531: ...GDMA CONTROLLER S3C2500B 12 24 NOTES ...
Страница 593: ...I O PORTS S3C2500B 15 12 NOTES ...