17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 791 of 1658
REJ09B0261-0100
17.3.4
Standby Display Register (MSTPMR)
MSTPMR is a 32-bit readable register that indicates whether the PCIC/display unit
(DU)/DMAC/GDTA modules are in the module standby state. MSTPMR can be accessed only in
longword.
This register is initialized by a power-on reset by the
PRESET
pin, power-on reset by WDT
overflow, or H-UDI reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
x
x
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
MSTP
MDU
MSTP
MPCI
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSTPS
100
⎯
⎯
⎯
MSTPS
104
MSTPS
105
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
31 to 22
⎯
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
21
MSTPMPCI x
R
Module Stop Display Bit PCIC
Indicates the state of clock supply to the PCIC module
When a high level signal is input to the MODE12 pin,
the clock supply to the PCIC is stopped
0: PCIC operates (MODE12 pin: Low level)
1: PCIC stopped (MODE12 pin: High level)
20
MSTPMDU
x
R
Module Stop Display Bit DU
Indicates the state of clock supply to the DU module.
When a low level signal is input to the MODE12 or
MODE11 pin, the clock supply to the DU is stopped.
0: DU operates (MODE[12:11] pin: All High level)
1: DU stopped (MODE[12:11] pin: Not all High level)
19 to 6
⎯
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Содержание SH7781
Страница 4: ...Rev 1 00 Jan 10 2008 Page iv of xxx REJ09B0261 0100 ...
Страница 74: ...2 Programming Model Rev 1 00 Jan 10 2008 Page 44 of 1658 REJ09B0261 0100 ...
Страница 272: ...8 Caches Rev 1 00 Jan 10 2008 Page 242 of 1658 REJ09B0261 0100 ...
Страница 376: ...10 Interrupt Controller INTC Rev 1 00 Jan 10 2008 Page 346 of 1658 REJ09B0261 0100 ...
Страница 694: ...13 PCI Controller PCIC Rev 1 00 Jan 10 2008 Page 664 of 1658 REJ09B0261 0100 ...
Страница 762: ...14 Direct Memory Access Controller DMAC Rev 1 00 Jan 10 2008 Page 732 of 1658 REJ09B0261 0100 ...
Страница 788: ...15 Clock Pulse Generator CPG Rev 1 00 Jan 10 2008 Page 758 of 1658 REJ09B0261 0100 ...
Страница 828: ...17 Power Down Mode Rev 1 00 Jan 10 2008 Page 798 of 1658 REJ09B0261 0100 ...
Страница 846: ...18 Timer Unit TMU Rev 1 00 Jan 10 2008 Page 816 of 1658 REJ09B0261 0100 ...
Страница 1292: ...24 Multimedia Card Interface MMCIF Rev 1 00 Jan 10 2008 Page 1262 of 1658 REJ09B0261 0100 ...
Страница 1326: ...25 Audio Codec Interface HAC Rev 1 00 Jan 10 2008 Page 1296 of 1658 REJ09B0261 0100 ...
Страница 1482: ...28 General Purpose I O Ports GPIO Rev 1 00 Jan 10 2008 Page 1452 of 1658 REJ09B0261 0100 ...
Страница 1538: ...30 User Debugging Interface H UDI Rev 1 00 Jan 10 2008 Page 1508 of 1658 REJ09B0261 0100 ...
Страница 1688: ...Appendix Rev 1 00 Jan 10 2008 Page 1658 of 1658 REJ09B0261 0100 ...
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Страница 1692: ...SH7785 Hardware Manual ...