12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 542 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
M
CS
M
R
A
S
M
C
A
S
M
W
E
MA[10]
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0]
Invalid
Invalid
Invalid
Invalid
READ
any
bank
Invalid
Invalid
Invalid
SDRAM
command
Invalid
Invalid
WRITE
any
bank
Write data
Read data
WRRD
= 7 cycles
Valid
Valid
Valid
Valid
Valid
Valid
Example of CL= 3
Hi
g
h level
Figure 12.19 WRITE-READ Minimum Time
Figure 12.19 is an example of a case in which, after issuing a WRITE command, a READ
command is issued. In order to issue the READ command after issuing the WRITE command, the
DBSC2 waits for a minimum time stipulated by the WRRD bits.
Содержание SH7781
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Страница 1482: ...28 General Purpose I O Ports GPIO Rev 1 00 Jan 10 2008 Page 1452 of 1658 REJ09B0261 0100 ...
Страница 1538: ...30 User Debugging Interface H UDI Rev 1 00 Jan 10 2008 Page 1508 of 1658 REJ09B0261 0100 ...
Страница 1688: ...Appendix Rev 1 00 Jan 10 2008 Page 1658 of 1658 REJ09B0261 0100 ...
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