12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 531 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
M
CS
M
R
A
S
M
C
A
S
M
W
E
MA[10]
ACT
bank A
bank A
Invalid
Invalid
Invalid
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0]
Invalid
Invalid
Invalid
SDRAM
command
Invalid
Invalid
Example of CL = 3
Valid
Valid
Valid
Valid
Valid
Valid
Hi
g
h level
READ
Read data
Figure 12.8 Waveforms for 1/2/4/8/16-Byte Reading
(When the Bus Width Is Set to 32 Bits)
Figure 12.9 shows waveforms for 32-byte reading when the bus width is set to 32 bits. In this case,
the READ command is issued twice. In this example, read access processing is executed for bank
A after the ACT command is issued, but when there is a page hit, access begins with the issue of
the READ command.
Содержание SH7781
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Страница 1482: ...28 General Purpose I O Ports GPIO Rev 1 00 Jan 10 2008 Page 1452 of 1658 REJ09B0261 0100 ...
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