Renesas M16C/62P Group, Руководство по оборудованию

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M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus
Rev.2.41 Jan 10, 2006 Page 63 of 390
REJ09B0185-0241
8.2.4 Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, BHE
and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When the data
bus is 8 bits wide, use a combination of RD, WR and BHE.
Table 8.3 shows the Operation of RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD, WRL,
and BHE Signals.
8.2.5 ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE
signal falls.
Figure 8.3 ALE Signal, Address Bus, Data Bus
Table 8.3 Operation of RD, WRL and WRH Signals
Data Bus Width
RD WRL WRH Status of External Data Bus
16-bit
(BYTE pin input = L) L H H Read data
H L H Write 1 byte of data to an even address
H H L Write 1 byte of data to an odd address
H L L Write data to both even and odd addresses
Table 8.4 Operation of RD, WRL and BHE Signals
Data Bus Width
RD WRL BHE A0 Status of External Data Bus
16-bit
(BYTE pin input = L) H L L H Write 1 byte of data to an odd address
L H L H Read 1 byte of data from an odd address
H L H L Write 1 byte of data to an even address
L H H L Read 1 byte of data from an even address
H L L L Write data to both even and odd addresses
L H L L Read data from both even and odd addresses
8-bit
(BYTE pin input = H) H L Not used H or L Write 1 byte of data
L H Not used H or L Read 1 byte of data
When BYTE Pin Input = H When BYTE Pin Input = L
ALE
Address Data
Address
(1)
A0/D0 to A7/D7
A8 to A19
ALE
Address Data
Address
A1/D0 to A8/D7
A9 to A19
Address
A0
NOTES :
1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
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