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M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
Rev.2.41
Jan 10, 2006
Page 293 of 390
REJ09B0185-0241
22.3.8
Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0
register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking
these bits (full status check).
Table 22.6 lists Errors and FMR0 Register State. Figure 22.14 shows a flow chart of the Full Status Check and
Handling Procedure for Each Error.
NOTES:
1. The flash memory enters read array mode by writing command code “xxFFh” in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to “1” (lock bit disabled), no error occurs even under the conditions
above.
Table 22.6
Errors and FMR0 Register State
FMR00 Register
(Status Register) State
Error
Error Occurrence Conditions
FMR07 bit
(SR5 bit)
FMR06 bit
(SR4 bit)
1
1
Command
Sequence error
• Command is written incorrectly
• A value other than “xxD0h” or “xxFFh” is written in the
second bus cycle of the lock bit program, block erase or
erase all unlocked block command
(1)
1
0
Erase error
• The block erase command is executed on a locked block
• The block erase or erase all unlocked block command is
executed on an unlock block and auto erase operation is
not completed as expected
(2)
0
1
Program error
• The program command is executed on locked blocks
• The program command is executed on unlocked blocks
but program operation is not completed as expected
• The lock bit program command is executed but program
operation is not completed as expected
(2)
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