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M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
Rev.2.41
Jan 10, 2006
Page 61 of 390
REJ09B0185-0241
Figure 8.1
CSR Register
Chip Select Control Register
Address
After Reset
0008h
00000001b
Bit Symbol
Function
RW
NOTES :
1.
2.
3.
Where the RDY
_____
signal is used in the area indicated by CSi
____
(i = 0 to 3) or the multiplex bus is used, set the CSiW bit to
(w ith w ait state).
If the PM17 bit in the PM1 register is set to “1” (w ith w ait state), set the CSiW bit to “0” (w ith w ait state).
When the CSiW bit = 0 (w ith w ait state), the number of w ait states can be selected using the CSEi1W to CSEi0W bits
in the CSE register.
RW
CS3W
0 : With w ait state
1 : Without w ait state
(1, 2, 3)
CS1
____
Wait Bit
CS2
____
Wait Bit
CS3
____
Wait Bit
CS2W
CS1W
RW
RW
CS1
CS2
CS3
CS0W
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RW
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
CS0
CS0
____
Output Enable Bit
Bit Name
CSR
RW
RW
RW
RW
CS0
____
Wait Bit
CS2
____
Output Enable Bit
CS1
____
Output Enable Bit
CS3
____
Output Enable Bit
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