Renesas IDT Tsi576, Руководство пользователя

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6. Event Notification > Port-write Notifications 137
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Table 15 shows the port write packet data payload for error reporting.
6.6.3 Servicing Port-writes
The Tsi576 supports a programming model for servicing port-writes. The first algorithm described
minimizes the number of port writes generated by the Tsi576, and therefore the number of specific
interrupt events that must be handled by a system host.
When a system host receives a port-write because of an event on Port N, the host follows these steps:
• Determine what error caused the port-write to be generated by going through “RapidIO Logical
and Transport Layer Error Detect CSR” on page 290 and the following registers of Port N:
— “RapidIO Port x Error and Status CSR” on page 280 (bits 6, 7, and 29)
— “RapidIO Port x Interrupt Status Register” on page 328
• Correct the error conditions and clear the error sources.
• Clear the PORT_W_PEND bit in the “RapidIO Port x Error and Status CSR” on page 280 .
In the case when there are other errors from other ports that have generated a port-write, bits in the
register
“RapidIO Port Write Outstanding Request Register” on page 395 are set.
Table 15: Port Write Packet Data Payload — Error Reporting
Data Payload
Byte Offset Word 0 Word 1
0x0 “RapidIO Component Tag CSR” on page 261 “RapidIO Port x
Error Detect CSR”
on page 296
for Port
ID
0x8 • Implementation specific bits ( “RapidIO Port x
Interrupt Status Register” on page 328 ):
— Bit 12: MC_TEA
— Bit 13: LINK_INIT_NOTIFICATION
— Bit 14: LUT_PAR_ERR bit
— Bit 15: OUTPUT_DEG bit
— Bit 16: OUTPUT_FAIL bit
— Bit 17: INB_RDR bit
— Bit 18: INB_DEPTH bit
— Bit 19: OUTB_DEPTH
— Bit 20: PORT_ERR
— Bit 21: ILL_TRANS_ERR
— Bit 22: OUTPUT_DROP
— Bit 23: MAX_RETRY
Port ID (8 bits)
(bits 24 to 31)
“RapidIO Logical and
Transport Layer
Error Detect CSR”
on page 290