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485

Tsi576 User Manual

June 6, 2016

Integrated Device Technology

www.idt.com

A. 

Serial RapidIO Protocol Overview

The 

RapidIO Physical Layer 1x/4x LP-Serial Specification

 addresses the physical layer requirements 

for devices utilizing an electrical serial connection medium. This specification defines a full duplex 
serial physical layer interface (link) between devices using unidirectional differential signals in each 
direction. Further, it allows ganging of four serial links for applications requiring higher link 
performance. It also defines a protocol for link management and packet transport over a link. 

RapidIO systems are comprised of end point processing elements and switch processing elements. The 
RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which 
includes the 

Logical

, 

Common

 

Transport

, and 

Physical

 layers. The Logical layer specifications define 

the operations and associated transactions by which end point processing elements communicate with 
each other. The Common Transport layer defines how transactions are routed from one end point 
processing element to another through switch processing elements. The Physical Layer defines how 
adjacent processing elements electrically connect to each other. RapidIO packets are formed through 
the combination of bit fields defined in the Logical, Common Transport, and Physical Layer 
specifications. TheTsi576 fully manages the end to end link on each port. 

A.1

Protocol

The RapidIO Physical Layer 1x/4x LP-Serial specification

 defines the protocol for packet delivery 

between serial RapidIO devices including packet and control symbol transmission, flow control, error 
management, and other device to device functions. A particular device may not implement all of the 
mode selectable features presented in the RapidIO specification.

The 1x/4x LP-Serial physical layer specification has the following properties:

•

Embeds the transmission clock with data using an 8B/10B encoding scheme.

•

Supports one serial differential pair, referred to as one lane, or four ganged serial differential pairs, 
referred to as four lanes, in each direction.

•

Allows switching packets between RapidIO 1x/4x LP-Serial Ports and RapidIO Physical Layer 
8/16 LP-LVDS ports without requiring packet manipulation.

•

Employs similar retry and error recovery protocols as the RapidIO Physical Layer 8/16 LP-LVDS 
specification.

•

Supports transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbit/s) 
per lane.

A.2

Packets

A RapidIO 1x/4x LP-Serial packet is formed by prefixing a 10-bit physical layer header to the 
combined RapidIO transport and logical layer bit fields followed by an appended 16-bit CRC field. 
The sum of all of the bit fields adds 20 bytes to the encapsulated data packet size. The maximum data 
field size is 256 bytes resulting in a maximum packet size of 276 bytes.

Содержание IDT Tsi576

Страница 1: ...IDT Tsi576 Serial RapidIO Switch User Manual June 6 2016 Titl...

Страница 2: ...n request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition o...

Страница 3: ...erface 28 1 5 Internal Switching Fabric ISF 30 1 6 Internal Register Bus AHB 30 1 7 I2C Interface 30 1 8 JTAG Interface 32 2 Serial RapidIO Interface 35 2 1 Overview 35 2 1 1 Features 35 2 1 2 Transac...

Страница 4: ...onfiguration 70 3 4 Clocking 70 3 4 1 Changing the Clock Speed 71 3 4 2 Changing the Clock Speed Through I2 C 72 3 5 Port Power Down 72 3 5 1 Default Configurations on Power Down 73 3 5 2 Special Cond...

Страница 5: ...05 5 1 5 Multicast Behavior Overview 106 5 1 6 Multicast Work Queue 107 5 1 7 Broadcast Buffers 107 5 2 Multicast Group Tables 110 5 2 1 Configuring Basic Associations 112 5 2 2 Configuring Multicast...

Страница 6: ...eral Addressing 152 7 4 6 Master Data Transactions 153 7 5 Tsi576 as I2 C Slave 153 7 5 1 Slave Clock Stretching 155 7 5 2 Slave Device Addressing 156 7 5 3 Slave Peripheral Addressing 156 7 5 4 Exter...

Страница 7: ...for Performance Measurements 194 8 3 1 Clock Speeds 194 8 3 2 Tsi576 ISF Arbitration Settings 194 8 3 3 Tsi576 RapidIO Transmission Scheduler Settings 195 8 3 4 Tsi576 RapidIO Buffer Watermark Select...

Страница 8: ...entity CAR 248 12 5 2 RapidIO Device Information CAR 249 12 5 3 RapidIO Assembly Identity CAR 250 12 5 4 RapidIO Assembly Information CAR 251 12 5 5 RapidIO Processing Element Features CAR 252 12 5 6...

Страница 9: ...and Debug 2 304 12 7 14 RapidIO Port x Packet Error Capture CSR 2 and Debug 3 304 12 7 15 RapidIO Port x Packet Error Capture CSR 3 and Debug 4 305 12 7 16 RapidIO Port x Error Rate CSR 306 12 7 17 Ra...

Страница 10: ...C x SerDes Configuration Global 374 12 10 7 SRIO MAC x SerDes Configuration GlobalB 378 12 10 8 SRIO MAC x Digital Loopback and Clock Selection Register 379 12 11 Internal Switching Fabric ISF Registe...

Страница 11: ...figuration Register 439 13 2 12 I2C Boot Control Register 442 13 2 13 Externally Visible I2C Internal Write Address Register 446 13 2 14 Externally Visible I2C Internal Write Data Register 447 13 2 15...

Страница 12: ...l Protocol 486 B Clocking 491 B 1 Line Rate Support 491 B 1 1 Register Requirements Using 125 MHz S_CLK for a 3 125 Gbps Link Rate 492 B 2 P_CLK Programming 495 B 2 1 RapidIO Specifications Directly A...

Страница 13: ...1 Figure 20 Multicast Operation Option 1 104 Figure 21 Multicast Operation Option 2 105 Figure 22 Multicast Packet Flow in the Tsi576 108 Figure 23 Relationship Representation 112 Figure 24 Completed...

Страница 14: ...Latency Illustration 190 Figure 44 Congestion and Detection Flowchart 199 Figure 45 Congestion Example 202 Figure 46 Register Access From JTAG Serial Data In 204 Figure 47 Register Access From JTAG S...

Страница 15: ...I2C Register Map 157 Table 18 Format for Boot Loadable EEPROM 173 Table 19 Sample EEPROM Loading Two Registers 173 Table 20 Sample EEPROM With Chaining 174 Table 21 I2C Error Handling 176 Table 22 I2C...

Страница 16: ...able 47 AC JTAG level programmed by ACJT_LVL 4 0 376 Table 48 SerDes Register Map 404 Table 49 I2C Register Map 417 Table 50 Master Operation Sequence 426 Table 51 Special Characters and Encoding 487...

Страница 17: ...ctive state of logic 0 or the lower voltage level and is denoted by a lowercase _b An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special char...

Страница 18: ...and is revised as required Formal Contains information about a final customer ready product and is available once the product is released to production Revision History June 6 2016 Formal Updated Res...

Страница 19: ...xt Script May 25 2012 Formal Updated the second step in Removing a Destination ID to Multicast Mask Association Updated the second paragraph in Payload Updated Port writes and Multicast Updated the re...

Страница 20: ...About this Document 20 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 21: ...g 40 Gbits s aggregate bandwidth The Tsi576 enables customers to develop systems with robust features and high performance at low cost The Tsi576 provides designers and architects with maximum scalabi...

Страница 22: ...p DSP and processor aggregation and connecting to network backplanes The Tsi576 provides traffic aggregation through packet prioritization when it is used with RapidIO enabled I O devices When it is i...

Страница 23: ...d to manage compression and decompression algorithms These DSPs are controlled by a local processor and all these components are linked together by a low power small form factor low latency multicast...

Страница 24: ...e the bit ordering of a 4x port to simplify PCB layout Transport Layer RapidIO Features Dedicated destination ID lookup table per port used to direct packets through the switch Supports both hierarchi...

Страница 25: ...system operation IEEE 1149 1 and 1149 6 boundary scan with register access Internal switching fabric ISF Full duplex 80 Gbps line rate non blocking switching fabric Prevents head of line blocking on e...

Страница 26: ...ebug packet generation and capture Multicast functionality described in RapidIO Interconnect Specification Revision 1 3 Part 11 Head of line blocking avoidance 1 2 2 Transaction Flow Overview Packets...

Страница 27: ...e 1 3 Multicast Engine The Tsi576 multicast functionality is compliant to the RapidIO Version 1 3 Part 11 Multicast Specification 1 3 1 Multicast Operation In a multicast operation packets are receive...

Страница 28: ...modes and bit error rate testing Even and odd number ports have different capabilities For ports that can operate in 4x mode the even numbered ports can operate in either 4x or 1x mode while odd numb...

Страница 29: ...ound bandwidth at 3 125 Gbps for a port configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization...

Страница 30: ...s AHB allows any RapidIO port to configure and maintain the entire device When the Tsi576 receives a RapidIO maintenance packet destined for itself it translates the packet into register read or write...

Страница 31: ...ROM or by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up t...

Страница 32: ...its device address without consideration for any other meaning General Call The general call address will be NACK d and the remainder of the transaction ignored up to a subsequent Restart or Stop 1 8...

Страница 33: ...1 Functional Overview JTAG Interface 33 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com Bypass Hi Z IDCODE Clamp User data select...

Страница 34: ...1 Functional Overview JTAG Interface 34 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 35: ...iant with the RapidIO Interconnect Specification Revision 1 3 This section describes the transport layer features common to all Tsi576 RapidIO interfaces The RapidIO interface has the following capabi...

Страница 36: ...kets to be transmitted from the ISF The integrity of packets forwarded through the ISF is retained by sending the CRC code received with the packet For more information on the input and ouput queues r...

Страница 37: ...ved However in both modes the egress port always operates in cut through mode the packet is immediately forwarded A copy of the packet is saved at the egress port so that it can be retransmitted shoul...

Страница 38: ...O Route Configuration DestID CSR on page 262 using the LRG_CFG_DESTID and CFG_DESTID fields the upper seven bits of the destination ID in the LRG_CFG_DESTID field is truncated The LUT of all the ports...

Страница 39: ...tID 15 8 BASE field in SPx_ROUTE_BASE Yes No Obtain egress port from GLOBAL LUT using DestID 15 8 Obtain egress port from LOCAL LUT using DestID 7 0 LUT entry mapped and egress port Port_Total Yes No...

Страница 40: ...rt x Mode CSR on page 312 2 3 3 Flat Mode A flat mode LUT is a table that maps destination IDs 0 to 511 to user selectable egress ports Destination IDs that fall outside this range are sent to the egr...

Страница 41: ...Attributes Default Port CSR on page 264 If the default port is unmapped the packet is discarded and the Tsi576 raises the IMP_SPEC_ERR bit in the RapidIO Port x Error Detect CSR on page 296 100 1FF 0...

Страница 42: ...nto Global LUT through the PORT field in the RIO_ROUTE_CFG_PORT register Tsi57x Tsi57x Tsi57x DSP DSP DSP DSP DestID 0x13 DestID 0x11 DestID 0x12 DestID 0x10 DestIDs accessible through this link 0x02x...

Страница 43: ...0x0002 or 0x02 is routed by the switch to output port 1 A destination ID of 0x0003 or 0x03 is routed out port 0 and destination IDs greater than 0x1FF are routed out port 4 Figure 8 Flat Mode LUT Conf...

Страница 44: ...r write this register to change the configuration of the destination ID Example One Adding a Lookup Table Entry In the following example routing is added for all ports to route destination ID 0x98 to...

Страница 45: ...0x54 2 3 4 Hierarchical Mode The hierarchical mode of operation of the LUT allows the full range of 65536 16 bit destination IDs to be mapped This mode is enabled by setting RIO_SP_MODE LUT_512 0 The...

Страница 46: ...ly advertises the switch can map 512 destination IDs This is due to the fact that RIO_LUT_SIZE is a register with global scope but the ports can be independently configured for either flat mode or hie...

Страница 47: ...ets A B C 00 FF 00 FF MSB of DestID Port LSB of DestID Port xx DestID LSB is loaded into Local LUT through the CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register DestID MSB is loaded into Global LU...

Страница 48: ...time before packet traffic starts w 0078 0x0A 3 Program the Global LUT with the MSB of the DEST_IDs to be routed using the following write operations W 11870 0x0 SP8_ROUTE_CFG_DESTID W 11874 0x9 SP8_...

Страница 49: ...red mode of operation 2 3 6 Lookup Table Parity Each entry in the lookup table is parity protected A LUT parity error is detected in an entry when an incoming packet causes the ingress port to read th...

Страница 50: ...the request queue The TEA error is reported through a port write and or an interrupt Programmable in the Fabric Control Register and the interrupt status can be checked in the Fabric Interrupt Status...

Страница 51: ...table entries must be programmed to a known value after reset to achieve predictable operation When a lookup table entry s parity is incorrect the lookup table entry is in a parity error state Table 2...

Страница 52: ...is to be sent parity errors are still detected and flagged if they occur Since the LUTs power up in a random state the occurrence of a LUT_PAR_ERR will be a random occurrence until all LUT entries ar...

Страница 53: ...y data associated with the request The maintenance response packet is generated by the Tsi576 using the success or failure of the access and data from a read operation CRC is computed and the packet i...

Страница 54: ...count is 0 Do not care Send port write and set interrupt if enabled Bit 8 in RapidIO Logical and Transport Layer Error Detect CSR Tsi576 is not an endpoint device Port Write Hop count is 0 Do not care...

Страница 55: ...ol and Reset Control Symbol Interrupt CSR on page 314 Additionally the logical OR of all per port Multicast Event interrupt status is available in both the MCS field in the RapidIO Port x Multicast Ev...

Страница 56: ...orts enabled to forward multicast control symbols then transmit an MCS see RapidIO Serial Port x Control CSR on page 283 The minimum time between two transitions on the MCES pin is 1 s For example whe...

Страница 57: ...es With the exception of maintenance packets the Tsi576 does not re compute CRC codes for packets The CRC code is forwarded with the packet across the ISF and the packet is transmitted with the same C...

Страница 58: ...of the inbound outbound and outstanding ACK_IDs 4 The system host instructs the Tsi576 to generate a link request to its link partner using the RapidIO Serial Port x Link Maintenance Request CSR on pa...

Страница 59: ...er packets other than maintenance requests responses may be sent by the Tsi576 INPUT_EN Controls whether packets other than maintenance requests responses may be received by the Tsi576 In RapidIO Port...

Страница 60: ...pendent Register to assert an interrupt or send port write transactions see RapidIO Port x Control Independent Register Once the system host is notified that a new component is inserted the LINK_INIT_...

Страница 61: ...l packets arriving from the ISF for transmission to flush any existing packets in the transmit and receive queues of the port and to prevent new packets from being received from the device about to be...

Страница 62: ...LINK_INIT_NOTIFICATION_EN in the RapidIO Port x Control Independent Register continues to be enabled When the component is removed lane synchronization and or lane alignment is lost The errors detect...

Страница 63: ...tual duration of the LOLS condition has no impact on the process once the link is re acquired Any packets transmitted to the Tsi576 are not acknowledged because the port is in input error stopped stat...

Страница 64: ...s reported in the PORT_ERR bit in the RapidIO Port x Error and Status CSR When the PORT_ERR bit is set and port writes are enabled a port write is generated If the dead link timer expires which the li...

Страница 65: ...ing of one even numbered port and one odd numbered port Each port has flexible testing features including multiple loopback modes and bit error rate testing Even and odd number ports have different ca...

Страница 66: ...bandwidth at 3 125 Gbps for a port configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization that...

Страница 67: ...0 SP0 1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x 3 Serial Port 3 SP3 1x 4 Serial Port 4 SP4 1x 5 Serial Port 5 SP5 1x 6 Serial Port 6 SP6 1x or 4x 7 Serial Port 7 SP7 1x 8 Serial Port 8 S...

Страница 68: ...e ports in the following manner serial ports 0 and 1 use MAC 0 ports 2 and 3 use MAC 2 etc Ports are grouped into pairs of N and N 1 where N is even Two configurations are possible on each 4x mode cap...

Страница 69: ...up with the new setting of the MAC_MODE bit The port width in use can be different from the pin selected width the pin indicates what the port was set to operate at while the registers show what it i...

Страница 70: ...ble in the INIT_PWIDTH field Software may need to manage ackID recovery for the link partner when changing port usage between lanes A and C 3 3 2 1 Degraded Link Mode When a 4x port has degraded to a...

Страница 71: ...apidIO Interconnect Specification Revision 1 3 requires the receive and transmit signals must operate at the same baud rate This means a port must transmit at the same clock rate that it receives with...

Страница 72: ...f the Tsi576 RapidIO ports can be powered down to minimize power consumption when the port is not required However port 0 has special power down requirements that must be followed see Special Conditio...

Страница 73: ...that port is reset to the default value The port write destinationID must be re written for the whole device after a port is shut down and restored Similarly multicast settings for the entire device...

Страница 74: ...r on page 379 To save power assert the SPn 1_PWRDN pin and or set the PWDN_X1 bit to 1 in the SRIO MAC x Digital Loopback and Clock Selection Register on page 379 If this bit is not set Port n 1 consu...

Страница 75: ...the odd numbered port does not have access to the PHY In order to decrease the power dissipation of the port the odd numbered port can be powered down in this configuration When the even numbered port...

Страница 76: ...lane swap setting for the entire device is controlled by two configuration pins SP_RX_SWAP and SP_TX_SWAP see Signals on page 217 Register fields SWAP_TX and SWAP_RX fields in the SRIO MAC x Digital L...

Страница 77: ...Operations on channels as supported by the MAC Channel Configuration registers always operate on the specific channels regardless of the lane swap settings for a MAC see SRIO MAC x SerDes Configurati...

Страница 78: ...a for calculating the TX_BOOST is shown in SRIO MAC x SerDes Configuration Channel 0 on page 365 Figure 14 Drive Strength and Equalization Waveform 3 7 2 Receive Equalization The received signal can b...

Страница 79: ...here each loopback is implemented in the Tsi576 Figure 15 Tsi576 Loopbacks Internal Switching Fabric Serial RapidIO Physical and Transport Layers Even numbered Ports 4x mode or 1x mode Odd Numbered Po...

Страница 80: ...o cause packets to loop back in this fashion configure the lookup tables LUTs so the destination IDs are destined for the incoming port For more information on LUT programming refer to Lookup Tables 3...

Страница 81: ...es Framing Depending on the type of testing required in the system the SerDes framing function might need to be disabled in the Tsi576 For example framing must be disabled if a BERT test is performed...

Страница 82: ...ixed Pattern based BERT Fixed pattern based BERT uses data in software configurable registers to send an alternating pattern of 10 bit 8B10B code groups Fixed pattern based BERT does not produce error...

Страница 83: ...X_ALIGN_EN bit in the SMACx_CFG_CH 0 3 register 3 9 4 Using PRBS Scripts for the Transmitters and Receivers IDT provides PRBS scripts in PRBS Scripts All of the PRBS scripts affect all of the ports th...

Страница 84: ...3 Serial RapidIO Electrical Interface Bit Error Rate Testing BERT 84 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 85: ...ge 88 4 1 Overview The Internal Switching Fabric ISF is the crossbar switching matrix at the core of the Tsi576 It transfers packets from ingress ports to egress ports and prioritizes traffic based on...

Страница 86: ...attempt to send a packet to the same egress port queuing is required at the ingress ports Special arbitration algorithms at both the ingress and egress sides of the fabric ensure that head of line blo...

Страница 87: ...ation appears near the front of a RapidIO packet Congestion Configuring a port for cut through mode does not guarantee that the packet is sent to the ISF immediately after the destination ID arrives f...

Страница 88: ...Figure 17 Only HOL packets at the ingress queues or broadcast buffers are considered for arbitration Figure 17 Egress Arbitration Weighted Round Robin and Strict Priority 4 3 1 Strict Priority Arbitra...

Страница 89: ...e same arbiter exists for each Priority Group Depending on the setting of WRR_EN the Multicast Traffic can participate in the Round Robin arbiter The WRR arbiter consists of a Round Robin arbiter whic...

Страница 90: ...s not reached Once the WEIGHT value is reached a non chosen packet is selected instead and the Chose Packet Counter is reset In the case when no chosen packet is available when its opportunity arises...

Страница 91: ...store the incoming packets when the egress port has a slower baud rate than the ingress port The depth of the buffer queue dictates the switch fabric flow control This flow control determines how man...

Страница 92: ...free buffers is greater than the programmed watermark of the associated priority For example when the PRIO1WM field is programmed to three a priority 1 packet is accepted only when there are four or m...

Страница 93: ...while one packet in the burst is being transmitted and is awaiting acknowledgment another packet in the burst cannot be accepted or transmitted Watermarks can be used to guarantee that two buffers ar...

Страница 94: ...er to Loss of Lane Synchronization on page 62 4 4 2 Input Queue for the ISF Port Each ingress port has a queue that holds up to eight packets Buffering is required to deal with any congestion in the I...

Страница 95: ...e HOL blocking can result HOL occurs when the packet at the head of a queue is blocked and the packets must remain in the same order This means that no packet in the queue can be sent across the ISF e...

Страница 96: ...iter selects a packet to compete in egress arbitration based on the following rules Select the priority 3 packet that can be accepted by its destination fabric port and is closest to the head of the q...

Страница 97: ...cket closest to the head of the queue Note that this packet cannot make progress Else if there are no such packets Select the priority 1 packet that can be accepted by its destination fabric port and...

Страница 98: ...er than Y that appear ahead of packet X in the queue must also be 0 Reorder limiting is disabled by default and can be enabled by setting the RDR_LIMIT_EN bit to 1 in the Fabric Control Register on pa...

Страница 99: ...rt on page 118 Any priority N packet is accepted before packets of priority N 1 Within each priority the multicast work queue uses the round robin algorithm The multicast work queue operates in strict...

Страница 100: ...ace for 8 more bytes of data to be received the multicast work queue is signalled that no more packet data can be accepted by the broadcast buffer If there is sufficient space for 8 more bytes of data...

Страница 101: ...s idles whenever the ingress port has not yet received data for transmission However during the transfer the egress port cannot receive information from ports other than the egress port Therefore when...

Страница 102: ...4 Internal Switching Fabric Packet Queuing 102 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 103: ...estinationID and Transaction Type TT field value If no match is found for the destinationID and TT field then the ingress lookup tables are used to route the packet A maximum of eight different DestID...

Страница 104: ...ultiple Tsi57x Switches Tsi57x multicast support is designed to allow information from a single source to be multicast efficiently over a tree topology within a RapidIO fabric see Figure 20 When two o...

Страница 105: ...multicast group is associated with a unique destinationID and TT of a packet Note A packet is never multicast back out of the port that it is received on regardless of whether or not this port is incl...

Страница 106: ...the Broadcast Buffers associated with the ports in the vector Transmission between the multicast work queue and the Broadcast Buffers uses a dedicated ISF path that is separate from those used to rou...

Страница 107: ...Timer on page 120 When the multicast work queue has computed the multicast vector it arbitrates to transmit packet copies to the broadcast buffers accordingly The work queue always operates in a cut...

Страница 108: ...a packet copy to the maximum value of seven For more information refer to Error Management of Multicast Packets on page 120 The following figure shows a step by step multicast operation through the T...

Страница 109: ...work queue operates in cut through mode 5 By consulting the multicast group table Ports 0 1 2 and 13 are identified as members of the vector and as the receiving ports Because Port 1 is the ingress p...

Страница 110: ...e 8 bit destination ID of five and the 16 bit destination ID of five requires two entries in the multicast group table If the destination ID contained in an incoming packet matches any of the eight en...

Страница 111: ...O Multicast DestID Configuration Register on page 267 and RapidIO Multicast DestID Association Register on page 268 To execute either of the previous two operations port removal or group deletion the...

Страница 112: ...quired 1 Set up the operation to associate destination ID 0x1234 with multicast mask 0 Write the value 0x1234_0000 to the RapidIO Multicast DestID Configuration Register on page 267 The individual ass...

Страница 113: ...is example the state of the multicast masks is unknown and therefore the masks must be cleared before being configured In order to clear the masks the following register accesses are made 1 Remove all...

Страница 114: ...The following figure shows the completed configuration Figure 24 Completed Tables at the End of Configuration Port Participating in Vector C B A 7 4 6 5 4 3 2 1 0 0 1 2 4 3 5 6 7 DEST_ID Large Small M...

Страница 115: ...Write the value 0x0002_0100 to the Multicast Mask Configuration Register Read the value 0x0002_0101 from the Multicast Mask Configuration Register 3 Verify that port 2 is included in mask 2 Write the...

Страница 116: ...ister 5 2 3 Configuring Multicast Masks Using the IDT Specific Registers The Tsi576 also has a device specific implementation to configuring the multicast masks This implementation allows the direct w...

Страница 117: ...l Multicast Mask Number 12 34 xx 44 0 1 Switch Port Number 0 No 1 Yes 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Multicast Write ID bits 16 31 in the RIO_MC_ID 0 7 registers Multicast...

Страница 118: ...one after the other to accept packets when available No one port can monopolize the RR arbiter When a port skips an opportunity to transmit because it carries no packet at the moment the RR arbiter d...

Страница 119: ...t 1 Packet RR Src Port 0 Packet Src Port 13 Packet Src Port 1 Packet RR Src Port 0 Packet Src Port 13 Packet Src Port 1 Packet Priority 3 Packets Priority 2 Packets Priority 1 Packets Priority 0 Packe...

Страница 120: ...he Tsi576 and a stomp control symbol is received part way though the packet the packet is still multicast to the egress ports However the egress ports stomp the packet when they transmit the packet 5...

Страница 121: ...latency timer expires in addition to packets being purged the port is removed from multicast operation By clearing the multicast latency timer error for that failed port the traffic from the MCE to t...

Страница 122: ...ort is powered down the port looses configuration information that is stored for that particular port For example multicast settings and port write settings return to their default power up settings a...

Страница 123: ...otifications on page 135 Interrupt Notifications on page 138 6 1 Overview The Tsi576 has the following ways to notify external devices about events occurring within the switch 1 Generate a RapidIO Por...

Страница 124: ...d port receives a transaction with one of the following errors Unmapped entry in LUT Reserved TT field value for data packet or maintenance packet with a hop count not equal to zero The status of this...

Страница 125: ...the RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page 314 as well as the MCS bit in the Global Interrupt Status Register RapidIO Yes No Outbound Queue Thres...

Страница 126: ...for link response The Dead Link Timer for a port has expired The Lane Sync Timer for at least one lane of the port has expired The status of this event is contained in the PORT_ERR bit of the RapidIO...

Страница 127: ...o link request is outstanding The status of this event is contained in the PROT_ERR bit of the RapidIO Port x Error Detect CSR on page 296 RapidIO Yes Yes1 Delineation Error Error This event is raised...

Страница 128: ...in the CS_NOT_ACC bit of the RapidIO Port x Error Detect CSR on page 296 RapidIO Yes Yes1 Packet CRC Error Error This event is raised when a RapidIO port receives a packet with a CRC error The status...

Страница 129: ...ery tick of the Error Rate Bias Timer The counts do not decrement below 0 This field only tracks transmission errors that have been unmasked in the Port x Error Rate Enable CSR This counter does not m...

Страница 130: ...r the method described in this section uses IDT specific functionality and control symbols to clear the errors by forcing a hardware recovery situation through software 6 4 1 Error Stopped States An I...

Страница 131: ...lear error conditions is to create a situation that forces the hardware recovery process to run again This situation is created by sending a control symbol to a link partner that the partner can respo...

Страница 132: ...r sends a Packet not accepted General Error Link Request Input Status control symbol To cause the transmission of the required control symbol write the value 0x40FC8000 to the RapidIO Port x Control S...

Страница 133: ...any of the illegal transaction maximum retry lookup table parity error or time to live events occur regardless of whether they are enabled or not When most of the errors listed in Table 14 occur they...

Страница 134: ...received not the packet that was retried Yes Received corrupt control symbol Received a control symbol with a bad CRC value The status of this error is contained in the CS_CRC_ERR bit in the RapidIO P...

Страница 135: ...t does not have a guaranteed delivery and does not have an associated response see RapidIO Interconnect Specification Revision 1 3 Depending on system design a port write can be sent repeatedly until...

Страница 136: ...untered the error condition and implementation specific information The layout of the port write packet is shown in the Table 15 on page 137 Port writes are sent at the priority defined in the PW_PRIO...

Страница 137: ...s 6 7 and 29 RapidIO Port x Interrupt Status Register on page 328 Correct the error conditions and clear the error sources Clear the PORT_W_PEND bit in the RapidIO Port x Error and Status CSR on page...

Страница 138: ...destinationID of the port write packet that is contained in the RapidIO Port Write Target Device ID CSR is also contained in a multicast group the port write will be routed to the multicast engine The...

Страница 139: ...SP_CTL_INDEP OUTPUT_DEG bit 7 SP_ERR_STATUS OUTPUT_FAIL bit 6 SP_ERR_STATUS TEA bit 31 SP_INT_STATUS TEA_EN bit 31 SP_CTL_INDEP MCT_TEA bit 13 SP_INT_STATUS MCT_TEA_EN bit 13 SP_CTL_INDEP LINK_INIT_N...

Страница 140: ...s not associated with any port Two functions that are port specific have separate indicator bits to allow for faster handling These functions are Multicast Event Control Symbol reception and reception...

Страница 141: ...or and Status Register Status Status Bit Further Information Interrupt Enable Interrupt Clearing OUTPUT_DROP RIO Serial Port x Control CSR RIO Port x Error Rate CSR RIO Port x Error Rate Threshold CSR...

Страница 142: ...ontrol Independent Register on page 321 controls whether any enabled interrupts are propagated to the Global Interrupt Status Register on page 390 to generate an interrupt If the IRQ_EN bit is disable...

Страница 143: ...slave serial interface that can be used for the following purposes Initializing device registers from an EEPROM after reset Reading and writing external devices on the I2 C bus Reading and writing Tsi...

Страница 144: ...r by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up to 100...

Страница 145: ...nsmitted from one device to another across the I2C_SD bus with timing referenced to the I2C_SCLK bus With some exceptions each bus can be driven low to a logic 0 by any device but is pulled high to a...

Страница 146: ...static signals from outside the block or connect to package pins for board level configuration The I2C_MA pin is a power up configuration pin that is latched during reset On the core side the I2C blo...

Страница 147: ...ternal I2C Device External I2C Device I2C_SD I2C_SCLK Master Interface Digital Filter Digital Filter Boot Load Sequencer Slave Interface Internal Register Bus Master Externally Visible Registers Event...

Страница 148: ...Rd 1 Slave Address Data Read from Device ReadData P R Restart loops to start of slave address sequence Stop ends the transaction bus is idle A Byte A Byte A Byte K A A K A A A A A N I2 C Write Data P...

Страница 149: ...protocol used by memory oriented devices such as EEPROMs involves the master sending one or more bytes of memory address to the slave to position the slave s memory address or peripheral address then...

Страница 150: ...rom I2C_MST_WDATA P S PerAdrMsb PerAdrLsb ReadData 7 Bit SlvAdr Wr 0 Slave Address Peripheral Address Data Read from Device ReadData A A A A A ReadData ReadData N A Arbitration Loss pa_size 2 pa_size...

Страница 151: ...ROM This example is configured in the context of register writes that must be made during a boot load of the EEPROM 7 4 1 1 Write Example Write 8 bytes to the EEPROM w 1d114 0x0042FFFF load the write...

Страница 152: ...Enable Register In this case the transaction is not automatically retried and it is up to software to retry if needed 7 4 5 Master Peripheral Addressing Some devices such as EEPROMs require a peripher...

Страница 153: ...MA_OK of the I2C Interrupt Enable Register 7 5 Tsi576 as I2 C Slave The Tsi576 can operate as a slave device on the I2C bus An external master device places a transaction on the bus with a device add...

Страница 154: ...ress space In addition either the SA_WRITE or SA_READ interrupt status is updated in the I2 C Interrupt Status Register if a read or write to the internal register space was triggered by the access An...

Страница 155: ...e bytes no defined limit Write Transaction Matched to SLV_ADDR Sets SLV_PA Data Written to Peripheral Space P R ReadData ReadData A A ReadData N Read Transaction Setting Peripheral Address Readdress f...

Страница 156: ...f 256 bytes from 0x00 to 0xFF that can be directly read and written by an external I2C master device When an external master sets the peripheral address this sets a pointer viewable in the SLV_PA fiel...

Страница 157: ...R W EXI2C_REG_WDATA Specifies the data to write to the internal register address held in EXI2C_REG_WADDR Side effects When address 0x07 the MSB is written the data in this register is written to the i...

Страница 158: ...ng mailboxes and on the state of the alert response flag 0x24 0x27 R W EXI2C_ACC_CNTRL Provides control information on how the Tsi576 handles internal register accesses through the EXI2C_REG_RDATA and...

Страница 159: ...gister read operation is completed the data is first loaded into the Externally Visible I2C Internal Read Data Register then returned to the external I2C master byte by byte The Externally Visible I2C...

Страница 160: ...transactions The following conditions pre exist ALERT_FLAG is set in the Externally Visible I2C Slave Access Status Register 1 External device reads Externally Visible I2C Slave Access Status Register...

Страница 161: ...2 C Slave Access Status Register then does another Alert Response request The ALERT_FLAG is zero all enables were cleared so the alert response address is NACKed I2 C Sequence S SLVA W PA 0x84 A WD 0x...

Страница 162: ...tic Timer I2C_BOOT_DIAG_TIMER is 0x8000BBCC reserved fields stay zero and interrupt status SA_OK and SA_WRITE assert An optional interrupt can also be sent to the Interrupt Controller if enabled in th...

Страница 163: ...lly Visible I2 C Internal Read Address Register is0x001D354 and interrupt status SA_OK and SA_READ assert An optional interrupt can also be sent to the Interrupt Controller if enabled in SA_OK and SA_...

Страница 164: ...registers are discussed further in the following sections EXI2C_MBOX_IN Writes to Mailbox 0100 000111 EXI2C_MBOX_IN EXTERNAL I2 C MASTER Flag Goes Up EXI2C_ACC_STAT IMB_FLAG Host is Interrupted IMB_F...

Страница 165: ...ternally Visible I2C Slave Access Status Register which the external I2C master can poll through the slave interface When the flag goes up 1 the external I2 C master reads the outgoing mailbox registe...

Страница 166: ...col as a SMBus host device in slave mode 7 7 2 SMBus Protocol Support The Tsi576 master interface functionality supports a subset of the SMBus Protocols see Figure 36 In all cases the Tsi576 masters a...

Страница 167: ..._SIZE 0 SIZE 0 WRITE 0 SMBus Write Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 1 SMBus Write Word PA_SIZE 1 SIZE 2 DORDER 1 WRITE 1 SMBus Read Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 0 SMBus Read Word PA_SIZE 1...

Страница 168: ...see Power up Options in this document This data initializes the Tsi576 s internal registers The boot load sequence occurs only after a full chip reset and follows the steps shown in Figure 38 The boo...

Страница 169: ...Info Per Address Select next device Boot Init and Device Detect Set Register Count Peripheral Address Read Register Count from the first 2 bytes of the EEPROM after reset Set Register Info Peripheral...

Страница 170: ...al low preventing the generation of a STOP or START condition To try to force these devices out of their hung state the Tsi576 allows the I2C_SD signal to stay high and generate 9 clock pulses on the...

Страница 171: ...pt status is updated in the I2C Interrupt Status Register On these boot load status bits the optional interrupt can be forwarded to the Interrupt Controller if enabled in the I2C Interrupt Enable Regi...

Страница 172: ...gister It may also be necessary to use the BOOT_UNLK field to change the lower 2 bits of the EEPROM address By default the BOOT_UNLK field is not set so if the BOOT_ADDR field is changed the lower 2 b...

Страница 173: ...er Transmit Data Register at internal address 0x1D114 loaded with data value 0x0506_0708 Table 18 Format for Boot Loadable EEPROM PerAdr PerAdr 0 PerAdr 1 PerAdr 2 PerAdr 3 0x0 RegCnt MSB RegCnt LSB 0...

Страница 174: ...haining operations The clocking speeds of the master devices Because many of these parameters are outside the control of the Tsi576 the boot time cannot be predicted with complete accuracy Table 20 Sa...

Страница 175: ...ime is a design concern the following techniques may accelerate the boot load sequence 1 If the EEPROM supports reading of a large block of data sequentially change PAGE_MODE in I2C Boot Control Regis...

Страница 176: ...d or write access during slave address phase or peripheral address phase or any write access during the data phase Access aborted STOP generated The I2C_ACC_STAT register indicates where transaction w...

Страница 177: ...and another device holds the signal to 0 Slave releases I2C_SD and I2C_SCLK goes into wait state SA_FAIL SCOL Register Initialization Loader Errors Failed to find EEPROM Initialization read Read opera...

Страница 178: ...t Generation The interrupt status bits are cleared by a write one to clear operation to the Interrupt Status Register provided the interrupt status register has first been read For test purposes bits...

Страница 179: ...tatus bit The combined event state becomes the interrupt status bit in the Interrupt Status Register and is then anded with the corresponding enable in the I2C Interrupt Enable Register All the enable...

Страница 180: ...FULL Incoming Mailbox Full IMBW Incoming Mailbox Write Event BL_FAIL Boot Load Fail BLTO Boot Load Timeout Error BLERR Boot Load Error Event BLSZ Boot Load Size Error Event BLNOD Boot Load No Device E...

Страница 181: ...to their monitor for bus idle phase It is up to software to decide how to handle this error Because any operation was aborted without correct termination no Stop it is possible that the external devi...

Страница 182: ...plete If an ACK or NACK is successfully received the master continues as if the timeout had not expired If another I2 C master collides with Slave Address the timeout immediately takes effect followin...

Страница 183: ...has not completed in a reasonable time This could occur if the EEPROM was improperly programmed with an infinite chaining loop the bus ownership is held by some other device or some other anomalous si...

Страница 184: ...ion Timeout Master or Slave PerAdr or Data A N R P Wait for Bus Idle S Boot Adr A N W Boot Timeout Master Only Load Regs P Idle Detect EEPROM Reset Chain Load Regs START PerAdr P From SCL sampled low...

Страница 185: ...e not guaranteed to conform to the I2C Specification because of the absence of Schmitt triggers on the input of the I2C_SD and I2C_SCLK signals and the absence of slope controlled outputs for the I2C_...

Страница 186: ...ams I2C_SCLK START RESTART Condition Setup I2C_SD Hold I2C_SCLK STOP Condition Setup I2C_SD I2C_SCLK I2C_SD Data Bit or Ack Nack Setup I2C_SD Hold SCL Minimum Low I2C_SCLK High Low Minimum High Nomina...

Страница 187: ...re is no separate Stop Hold parameter as the only valid condition following a Stop would be a Start therefore the Start Setup fulfills the same use as a Stop Hold or Stop to Start buffer time This par...

Страница 188: ...the low period than the nominal low period the high period nominal timer will likely expire early and the minimum high period timer will control the high period when the clock is finally released 7 1...

Страница 189: ...fied for a single switch Performance for larger systems can be computed from this data 8 1 1 Throughput Throughput for packets is a measurement of the amount of packet data that can be transferred in...

Страница 190: ...ency figure that each packet experiences difficult because the amount of contention that a packet experiences can vary widely As such these scenarios are not covered in this manual Figure 43 Latency I...

Страница 191: ...rformance Statistics Counter 0 and 1 Control Register on page 334 RapidIO Port x Performance Statistics Counter 0 Register on page 346 Any of the performance statistics counter registers can be config...

Страница 192: ...ket size is COUNTER A divided by the value in COUNTER B 3 Utilization packet rate packet size max capacity Utilization is calculated using parameter 1 and parameter 2 above These values are derived fr...

Страница 193: ...Register on page 354 RapidIO Port x Transmitter Output Queue Congestion Period Register on page 356 The registers in the inbound direction are RapidIO Port x Receiver Input Queue Depth Threshold Regis...

Страница 194: ...t the lower the throughput the higher the average latency and the greater the spread between minimum and maximum latency For ports operating in 1x mode performance measurements are specified for opera...

Страница 195: ...pidIO egress buffer management For high priority configurations watermark settings should be used which deliver maximal throughput for the highest priority packets For ingress and egress ports a maxim...

Страница 196: ...intain the line rates This means there is no retry of packets at the ingress ports and no bubbles will appear in the egress packet stream except for the idle sequence insertion every 5000 code groups...

Страница 197: ...ance Under a non congested one port to many ports packet traffic scenario when the ingress line rate is the same as the total egress line rates for example one 4x mode 3 125 Gbaud ingress port splitti...

Страница 198: ...st engine retries occur at the ingress port In this situation the egress port maintains its line rate For example when an egress port is set to 4x mode 2 5 Gbaud while the multicast engine is receivin...

Страница 199: ...er by 1 Yes No Leak Rate timer expire Congestion Period timer expire Yes Yes No No Increment Congestion Period Counter by 1 Yes No Clear Congestion Period Counter Congestion Period Counter read by sof...

Страница 200: ...CONG_PERIOD_CTR This is the Congestion Period Counter This counter is incremented at every tick whose period is set by the CONG_PERIOD field when the Congestion Counter is greater than zero This regis...

Страница 201: ...status Both interrupts are located in the RapidIO Port x Interrupt Status Register on page 328 for the port The Congestion Counter and Congestion Period Counter fields must be polled in order to dete...

Страница 202: ...ion Period Count value see RapidIO Port x Transmitter Output Queue Depth Threshold Register on page 352 and the Congestion Counter value see RapidIO Port x Transmitter Output Queue Congestion Status R...

Страница 203: ...re are five standard pins associated with the interface TMS TCK TDI TDO and TRST_b which allow full control of the internal TAP Test Access Port controller The JTAG Interface has the following feature...

Страница 204: ...ing down the normal traffic in the device or during initialization A user defined command is used to enable the read and write capabilities of the interface The command is in the IEEE 1149 1 Instructi...

Страница 205: ...at are being shifted out as the first two bits shifted out 5 Go back to step two to perform another write 9 3 3 Read Access to Registers from the JTAG Interface The following steps are required in ord...

Страница 206: ...9 JTAG Interface JTAG Register Access Details 206 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 207: ...ation Clocks on page 207 Resets on page 211 Power up Options on page 214 10 1 Clocks The Tsi576 has three input clocks S_CLK_p n P_CLK and I2C_SCLK that are used to produce the Tsi576 s internal clock...

Страница 208: ...one RXCLKA or two RXCLKA B clocks are recovered On the transmit side the clock TX_CLK is derived from the SerDes An extra clock SYS_CLK is also sourced from the SerDes to the MAC The S_CLK_p n signal...

Страница 209: ...1 3 Reference clocks The two reference clocks are described in Table 26 Tip For information on configuring the clock rate of RapidIO ports refer to Clocking on page 70 Table 26 Tsi576 Input Reference...

Страница 210: ...P_CLK Programming on page 495 100 MHz This clock domain includes all internal registers within each of the internal blocks as well as the bus that performs the register accesses The domain uses the i...

Страница 211: ...ble for performing automatic reads from an externally attached EEPROM device in order to load the initial configuration of the device For more details refer to I2C Interface on page 143 10 2 1 2 HARD_...

Страница 212: ...tion of the self reset which is at least four P_CLK clock cycles If the SELF_RST field is not set an interrupt signal is asserted if RCS_INT_EN is also set in the RapidIO Port x Mode CSR on page 312 S...

Страница 213: ...device is dropped and any traffic still in flight to the peer device is dropped 4 Use the RapidIO Serial Port x Link Maintenance Request CSR on page 275 to transmit four reset control symbols in a row...

Страница 214: ...wer down SPn_PWRDN mode selection SPn_MODESEL lane swap SP_RX_SWAP and SP_TX_SWAP and I2 C pins I2c_DISABLE I2C_MA I2C_SA 1 0 I2C_SEL 10 3 1 Power up Option Signals Power up options are latched at res...

Страница 215: ...bility of this pin is only used in test mode SP n _PWRDN Port n Transmit and Receive Power Down Control This signal controls the state of Port n and Port n 1 The PWRDN controls the state of all four l...

Страница 216: ...when driven low single byte peripheral address is assumed I2C_SA 1 0 I2 C Slave Address pins The values on these two pins represent the values for the lower 2 bits of the 7 bit address of Tsi576 when...

Страница 217: ...fix _p are the positive half of a differential pair Signals with the suffix _n are the negative half of a differential pair Signals with the suffix _b are active low Signals are classified according t...

Страница 218: ...rts and in numerous register configuration fields Core Power Core supply Core Ground Ground for core logic I O Power I O supply N C No connect These signals must be left unconnected Table 30 Tsi576 Po...

Страница 219: ...ial Port 11 SP11 1x 12 Serial Port 12 SP12 1x 13 Serial Port 13 SP13 1x 14 Serial Port 14 SP14 Unavailable This port is un initialized and the port registers must be treated as reserved Writes to port...

Страница 220: ...ontrol symbol 2 REF_AVDD SP_IO_SPEED 1 0 Port Config 2 Ports 0 2 4 6 10 12 SP_VDD SP 2 4 10 12 _T A B _ p n 16 SP_VDD SP0_T A B C D _ p n SP0_R A B C D _ p n SP0_REXT 8 8 SP0_MODESEL 1 1 SP1_PWRDN 1 S...

Страница 221: ...mode Port n 1 Lane B Differential Non inverting Transmit Data output 1x mode No termination required SP n _TB_n O SRIO Port n Lane B Differential Inverting Transmit Data output 4x mode Port n 1 Lane B...

Страница 222: ...eive Data input 4x mode DC blocking capacitor of 0 1uF in series SP 0 6 _RD_n I SRIO Port n Lane D Differential Inverting Receive Data input 4x mode DC blocking capacitor of 0 1uF in series Serial Por...

Страница 223: ...configuration Either a 10K pull up to VDD_IO or a 10K pull down to VSS_IO Internal pull up can be used for logic 1 SP n 1 _PWRDN I O LVTTL PU Port n 1 Transmit and Receive Power Down Control This sign...

Страница 224: ...er to be sampled correctly These signals are ignored after reset and software is able to over ride the port frequency setting in the SRIO MAC x Digital Loopback and Clock Selection Register on page 37...

Страница 225: ...SWAP I LVTTL PD Configures the order of 4x transmit lanes on serial ports 0 6 0 A B C D 1 D C B A Must remain stable for 10 P_CLK cycles after HARD_RST_b is de asserted in order to be sampled correctl...

Страница 226: ...RapidIO link If self reset is not selected this pin remains asserted until the reset request is cleared from the status registers If self reset is selected this pin remains asserted until the self re...

Страница 227: ...signal does not control the slave accessibility of the interface This signal is ignored after reset No termination required Pull up to VDD_IO through a 10K resistor if I2 C loading is not required I2C...

Страница 228: ...utput No connect if JTAG is not used Pull up to VDD_IO through a 10K resistor if used TMS I LVTTL PU IEEE 1149 1 1149 6 Test Access Port Test Mode Select Pull up to VDD_IO through a 10K resistor if no...

Страница 229: ...Manual for more information Common Supply VDD_IO Common 3 3V supply for LVTTL I O Refer to decoupling recommendations in the Tsi576 Hardware Manual for more information VSS Common ground returns for d...

Страница 230: ...11 Signals Pinlist and Ballmap 230 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 231: ...egisters on page 382 Utility Unit Registers on page 390 Multicast Registers on page 397 SerDes Per Lane Register on page 404 12 1 Overview The application defined Tsi576 registers receive initial valu...

Страница 232: ...8 to 13 2 a read modify write operation must be performed for register reserved fields that have an undefined reset value Other reserved fields should always be written as 0 unless otherwise noted Ta...

Страница 233: ...1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x 3 Serial Port 3 SP3 1x 4 Serial Port 4 SP4 1x 5 Serial Port 5 SP5 1x 6 Serial Port 6 SP6 1x or 4x 7 Serial Port 7 SP7 1x 8 Serial Port 8 SP8 Una...

Страница 234: ...ce number refers to a RapidIO port number The special instance BC broadcast refers to a register that when written simultaneously affects all powered up ports and that when read returns a value from p...

Страница 235: ...Extension Registers on page 287 0x01000 0x0143C Reserved 0x014C0 0x0FFFF IDT Specific RapidIO Registers on page 309 and Serial Port Electrical Layer Registers 0x10000 0x14FFC Reserved 0x15000 0x1A9FC...

Страница 236: ...ch Multicast Support CAR on page 257 00034 RIO_LUT_SIZE RapidIO Route LUT Size CAR on page 258 00038 RIO_SW_MC_INFO RapidIO Switch Multicast Information CAR on page 259 0003C 00064 Reserved 00068 RIO_...

Страница 237: ...RapidIO Switch Port General Control CSR on page 274 Serial Port 0 Registers Offset 0x140 0x15C 00140 SP0_LM_REQ RapidIO Serial Port x Link Maintenance Request CSR on page 275 00144 SP0_LM_RESP RapidI...

Страница 238: ...ized 320 33C Serial Port 15 Tsi576 un initialized 340 FFC Tsi576 Reserved RapidIO Error Management Extensions General Error Management Registers 01000 RIO_ERR_RPT_BH RapidIO Error Reporting Block Head...

Страница 239: ...SR and Debug 0 on page 301 0104C SP0_ERR_ATTR_CAPT_0_DBG1 RapidIO Port x Packet and Control Symbol Error Capture CSR 0 and Debug 1 on page 303 01050 SP0_ERR_ATTR_CAPT_1_DBG2 RapidIO Port x Packet Erro...

Страница 240: ...l Port 15 Tsi576 un initialized 01440 0FFFC Tsi576 Reserved IDT Specific RapidIO Registers Broadcast Registers Offset 10000 10FFC Writing these registers affects all ports Read data comes from port SP...

Страница 241: ...ort 0 Same set of registers as Broadcast Registers offset 10000 100FC 11100 111FC Serial Port 1 11200 112FC Serial Port 2 11300 113FC Serial Port 3 11400 114FC Serial Port 4 11500 115FC Serial Port 5...

Страница 242: ...8 SP0_PSC4n5_CTRL RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 342 1302C 1303C Reserved 13040 SP0_PSC0 RapidIO Port x Performance Statistics Counter 0 Register on pag...

Страница 243: ...x SerDes Configuration Global on page 374 130C8 SMAC0_DLOOP_CLK_SEL SRIO MAC x Digital Loopback and Clock Selection Register on page 379 130CC Reserved 130D0 MCES_PIN_CTRL MCES Pin Control Register on...

Страница 244: ...s 0x13000 0x130FC 13F00 13FAC Serial Port 15 Tsi576 un initialized Same set of registers as for SP0 offsets 0x13000 0x130AC The registers at offsets 0x130B0 0x130FC are excluded Fabric Global Interrup...

Страница 245: ...0 1B0FC Reserved 1B100 1B1FC Serial Port 1 Same set of registers as Serial Port 0 offset 1B000 1B0FC 1B200 1B2FC Serial Port 2 1B300 1B3FC Serial Port 3 1B400 1B4FC Serial Port 4 1B500 1B5FC Serial Po...

Страница 246: ..._PM_CTL_1 SerDes Lane 1 Pattern Matcher Control Register on page 410 1E074 SMAC 0 2 4 6 _FP_VAL_1 SerDes Lane 1 Frequency and Phase Value Register on page 414 1E078 1E07C Reserved 1E0A0 SMAC 0 2 4 6 _...

Страница 247: ...registers are organized and accessed in the same way as the CARs All of the registers in this section are defined in the RapidIO Interconnect Specification Revision 1 3 These registers are reset by th...

Страница 248: ...0000 Bits 0 1 2 3 4 5 6 7 00 7 DEV_ID 07 15 DEV_ID 16 23 DEV_VEN_ID 24 31 DEV_VEN_ID Bits Name Description Type Reset Value 0 15 DEV_ID Device Identifier This field contains the IDT assigned part numb...

Страница 249: ...ue 0x0000_0010 Register offset 00004 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 SILICON_REV METAL_REV Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 27 SI...

Страница 250: ...O_ASBLY_ID Reset value 0x0001_000D Register offset 00008 Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_ID 08 15 ASBLY_ID 16 23 ASBLY_VEN_ID 24 31 ASBLY_VEN_ID Bits Name Description Type Reset Value 0 15 ASBLY_ID A...

Страница 251: ...SBLY_INFO Reset value 0x0000_0100 Register offset 0000C Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_REV 08 15 ASBLY_REV 16 23 EXT_FEAT_PTR 24 31 EXT_FEAT_PTR Bits Name Description Type Reset Value 0 15 ASBLY_REV...

Страница 252: ...reads and writes 1 The processing element has physically addressable local address space and can be accessed as an endpoint through non maintenance that is NREAD and NWRITE transactions R 0 2 PROC Pro...

Страница 253: ...guration of the ingress port s lookup table This bit is not used in the control of any functionality in the Tsi576 0 Device supports 8 bit destination IDs only 1 Device supports 8 bit and 16 bit desti...

Страница 254: ...et Value 0 15 Reserved N A R 0x0000 16 23 PORT_TOTAL Port Total The total number of RapidIO ports on the device Note that the number of ports reported in this register assumes that all RapidIO ports a...

Страница 255: ...15 Reserved IMPLEMENT_DEF 16 23 READ WRITE STRM_WR WR_RES D_MSG DBELL Reserved A_TSWAP 24 31 A_INC A_DEC A_SET A_CLEAR Reserved PORT_WR Reserved Bits Name Description Type Reset Value 0 13 Reserved N...

Страница 256: ...sters 256 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com 29 PORT_WR Port write operation The RapidIO ports support port write generation to report errors R 1 30 31 Reserved Im...

Страница 257: ...oes not support the simple programming model for more information see the RapidIO Multicast Mask Configuration Register on page 265 Register name RIO_PE_MC_FEAT Reset value 0x0000_0000 Register offset...

Страница 258: ...ination IDs with limited capabilities Register name RIO_LUT_SIZE Reset value 0x0000_01FF Register offset 0034 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 LUT_SIZE 0 7 24 31 LUT_SIZE 8 15...

Страница 259: ...ociation between a destinationID and a multicast mask 1 Block association is supported Not implemented in the Tsi576 R 0 1 ASSOC_SCOPE Defines the capabilities of a switch to associate a destination I...

Страница 260: ...FFF Note that writing 0xFFFF to this register does not result in a lock being obtained After writing the HOST_BASE_ID field a processing element must read the Host Base Device ID Lock CSR to verify th...

Страница 261: ...dIO Component Tag CSR This register is written by software It is used for labeling and identifying the port write transactions to the host Register name RIO_COMP_TAG Reset value 0x0000_0000 Register o...

Страница 262: ...per port configuration registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs usin...

Страница 263: ...ion registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs using this register refe...

Страница 264: ...078 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 DEFAULT_PORT Bits Name Description Type Reset Value 0 23 Reserved Reserved R 0 24 31 DEFAULT_ PORT Default Output Port All t...

Страница 265: ...UM 7 0 24 31 Reserved MASK_CMD Reserved PORT_ PRESENT Bits Name Description Type Reset Value 0 15 MC_MASK_NUM Specifies the multicast mask 0 7 which is to be modified when this register is written wit...

Страница 266: ...Multicast Mask 010 Delete the given Egress_Port_Number from the specified Multicast Mask 011 Reserved 100 Delete all egress ports from the specified Multicast Mask 101 Add all egress ports to the spec...

Страница 267: ...IDs to ranges of masks is not supported Register name RIO_MC_DESTID_CFG Reset value 0x0000_0000 Register offset 00084 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_BASE_LT 7 0 08 15 DESTID_BASE 7 0 16 23 MASK_NU...

Страница 268: ...ulticast mask or which association must be removed Register name RIO_MC_DESTID_ASSOC Reset value 0x0000_0000 Register offset 00088 Bits 0 1 2 3 4 5 6 7 00 07 ASSOC_BLK_SIZE 08 15 ASSOC_BLK_SIZE 16 23...

Страница 269: ...on Register 11 Add Associations This register write adds associations between a destination ID and multicast mask number The multicast mask number and destination ID are specified by a prior write to...

Страница 270: ...lds and some read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 143 for more information on the use of I2 C controller register loading capability Read...

Страница 271: ...idt com 8 0x0240 Tsi576 un initialized 9 0x0260 Tsi576 un initialized 10 0x0280 1x serial port 11 0x02A0 1x serial port 12 0x02C0 1x serial port 13 0x02E0 1x serial port 14 0x0300 Tsi576 un initializ...

Страница 272: ...block header information Register name RIO_SW_MB_HEAD Reset value 0x1000_0009 Register offset 100 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Description Type Res...

Страница 273: ...f 100 MHz When Link Time Out is expired the port enters the Output Error state as outlined in the RapidIO Interconnect Specification Revision 1 3 Register name RIO_SW_LT_CTL Reset value 0xFFFF_FF00 Re...

Страница 274: ...le through the Port General Control CSR of any other physical layer implemented on a device Register name RIO_SW_GEN_CTL Reset value 0x0000_0000 Register offset 13C Bits 0 1 2 3 4 5 6 7 00 07 Reserved...

Страница 275: ...request is outstanding and the CMD field is written to then the register write is ignored If this register is written twice in rapid succession it could cause a protocol violation If the RapidIO Seria...

Страница 276: ...cal Layer Registers 276 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com Writing to this register on a port in normal operation affects traffic on that port This register should...

Страница 277: ...T LINK_STAT Bits Name Description Type Reset Value 0 RESP_VLD Response Valid 0 No link response control symbol received or no link request reset transmitted 1 If the link request was a link request in...

Страница 278: ...to manually implement error recovery Note The INBOUND value can be initialized through the I2 C Interface Initializing the INBOUND value from I2 C is required for test purposes only Unless the INBOUN...

Страница 279: ...his register is being processed the OUTBOUND value is not used for the next packet transmitted The new OUTBOUND value is always used when the port is operating normally and when the port is in an erro...

Страница 280: ...T_ ERR PORT_ OK PORT_ UNINIT Bits Name Description Type Reset Value 0 4 Reserved N A R 0 5 OUTPUT_DROP Output port has discarded a packet The packet is dropped when the Error Rate Threshold is reached...

Страница 281: ...sibly recovered from a transmission error This bit is set when the Output Error stopped bit bit 15 is set R W1C 0 15 OUTPUT_ERR_ STOP Output Error stopped Outbound port is in the output error stopped...

Страница 282: ...able to recover fatal error The following fatal errors cause a PORT_ERR Four link request tries with link response but no outstanding ackID Four link request tries with time out error for link respons...

Страница 283: ...ROP_EN PORT_LO CKOUT PORT_TYP E Bits Name Description Type Reset Value 0 1 PORT_WIDTH Port Width This field displays the port mode after reset 00 Single lane port the port is 1x mode only 01 Four lane...

Страница 284: ...ependent Register on page 321 register Note Initial port width of the port is set by SPx_MODESEL pins at power up After reset release the SPx_MODESEL pins are ignored and configuration is controlled b...

Страница 285: ...control symbols out this port R W 0 13 Reserved N A R 0 14 ENUM_B Enumeration boundary bit used in system discovery algorithms This bit does not control any functionality within the Tsi576 The reset v...

Страница 286: ...orce the sending device to signal an error condition The receipt of a packet by the locked out port causes the assertion of the INPUT_ERR and INPUT_ERR_STOP bits in its RapidIO Port x Error and Status...

Страница 287: ...rmation on the use of I2C controller register loading capability The Logical Transport Error Detect registers are not required for a switch However a switch s register bus access errors and transport...

Страница 288: ...packets to the connected device if the Output Failed Encountered bit is set and or if the Error Rate Failed threshold has been met or exceeded 0 1 The port discards packets that receive a Packet not a...

Страница 289: ...gement Extensions registers in the Tsi576 Register name RIO_ERR_RPT_BH Reset value 0x0000_0007 Register offset 1000 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Des...

Страница 290: ...No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET Reset value 0x0000_0000 Register offset 1008 Bits 0 1 2 3 4 5 6 7 00 07 Reserved L_ILL_TRA NS Reserved 08 15 L_ILL_RE...

Страница 291: ...rrupts can be generated for these sources No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET_EN Reset value 0x0000_0000 Register offset 100C Bits 0 1 2 3 4 5 6 7 00 07...

Страница 292: ...ta can be captured in this register for erroneous port writes and maintenance responses as these transactions reserve the address field If the TT code for an erroneous maintenance request is invalid t...

Страница 293: ...t received For switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No other packets can reach the logical l...

Страница 294: ...ing the FTYPE field in the packet Note that for switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No othe...

Страница 295: ...its 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID_LSB 16 23 LARGE_ DESTID Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 DESTID_MSB Most Significant Byte of port write Target Devic...

Страница 296: ...99 When the threshold is reached hardware informs the system software of the error using its standard error reporting function After the error has been reported the system software can read and clear...

Страница 297: ...TEA MC_TEA LUT_PAR_ERR ILL_TRANS_ERR Caution The Error Capture register information is only valid for Reserved Transport Type Detected errors and Unmapped DestID errors For the Max Retry errors the in...

Страница 298: ...a packet accepted control symbol for it and has moved to the next ACK_ID value This value can be found in the RapidIO Serial Port x Local ackID Status CSR on page 278 Therefore an ACK_ID mismatch has...

Страница 299: ...1384 13C4 1404 Bits 0 1 2 3 4 5 6 7 00 07 IMP_SPEC _ERR Reserved 08 15 Reserved CS_CRC_E RR_EN CS_ILL_ID _EN CS_NOT_A CC_EN PKT_ILL_A CKID_EN PKT_CRC_ ERR_EN PKT_ILL_S IZE_EN Reserved 16 23 Reserved 2...

Страница 300: ...bytes R W 0 15 25 Reserved N A R 0 26 LR_ACKID_ILL_ EN Enable error rate counting A received Link Response control symbol contains an ackID that is not outstanding R W 0 27 PROT_ERR_EN Enable error ra...

Страница 301: ...ERR_TYPE 08 15 Reserved 16 23 Reserved 24 31 Reserved VAL_CAPT Bits Name Description Type Reset Value 0 1 INFO_TYPE Type of information logged 00 Packet 01 Control Symbol and unaligned SC or PD or un...

Страница 302: ...t Error No 00001 to 00111 Bit 1 8 Reserved 01000 Bit 9 CS_CRC_ERR Control Symbol CRC Error Yes 01001 Bit 10 CS_ILL_ID Control Symbol Illegal ID Yes 01011 Bit 11 CS_NOT_ACC Control Symbol Not Accepted...

Страница 303: ...ror recovery and threshold function the RapidIO Port x Error Detect CSR on page 296 and the Port x Error Capture registers are also writable Software must clear the Capture Valid Info VAL_CAPT bit in...

Страница 304: ...1150 1190 11D0 1210 1250 1290 12D0 1310 1350 1390 13D0 1410 Bits 0 1 2 3 4 5 6 7 00 7 CAPT_1 0 7 8 15 CAPT_1 8 15 16 23 CAPT_1 16 23 24 31 CAPT_1 24 31 Bits Name Description Type Reset Value 0 31 CAP...

Страница 305: ...acket Error Capture CSR 3 and Debug 4 Register name SP 0 15 _ERR_CAPT_3_DBG4 Reset value 0x0000_0000 Register offset 1058 1098 10D8 1118 1158 1198 11D8 1218 1258 1298 12D8 1318 1358 1398 13D8 1418 Bit...

Страница 306: ...7 ERR_RB The Error Rate Bias value Register bus frequency 100 MHz 00 Do not decrement error rate counter 01 Decrement every 1 31ms 02 Decrement every 10 48ms 04 Decrement every 83 88ms 08 Decrement e...

Страница 307: ...rt This number is decremented by the Error Rate Bias function The counter cannot over or underflow and continue to increment or decrement as defined even if thresholds are met Software can reset this...

Страница 308: ...16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 ERR_RFT Error Rate Failed Threshold These bits provide the threshold value for reporting an error condition due to a possibly b...

Страница 309: ...ity on boot Refer to I2 C Interface on page 143 for more information on the use of I2 C controller register loading capability When a individual port is powered down the IDT Specific RapidIO Registers...

Страница 310: ...formance Registers Port Register Offset Description SP0 13000 1x 4x mode serial port SP1 13100 1x mode serial port SP2 13200 1x mode serial port SP3 13300 1x mode serial port SP4 13400 1x mode serial...

Страница 311: ...pe Reset Value 0 3 DISCOVERY_ TIMER Discovery Timer This field is used by serial ports configured to operate in 4x mode The discovery timer allows time for the link partner to enter its discovery stat...

Страница 312: ..._ INT_EN Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 IDLE_ERR_DIS Idle Error Checking Disable 0 Error checking is enabled by default if one or more data characters are sent Dx y char...

Страница 313: ...f 256 destination IDs 1 One 512 entry local LUT R W 1 8 29 Reserved N A R 0 30 MCS_INT_EN Multicast Event Control Symbol Interrupt Enable 0 Disabled 1 Enabled The interrupt signal is high when the mul...

Страница 314: ...Interrupt Status Indicates whether a multicast event control symbol has been received on the port Reading the MCS field using the BC offset gives the value of Port 0 All MCS interrupts from ports are...

Страница 315: ...13 15 PRIO2WM Priority 2 packets are accepted if the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either...

Страница 316: ...T_ID 0 7 24 31 CFG_DEST_ID 8 15 Bits Name Description Type Reset Value 0 AUTO_INC Automatically post increment the destination ID when the destination ID is used to perform either a read or a write th...

Страница 317: ...ation Register name SP BC 0 15 _ROUTE_CFG_PORT Reset value Undefined Register offset 10074 11074 11174 11274 11374 11474 11574 11674 11774 11874 11974 11A74 11B74 11C74 11D74 11E74 11F74 Bits 0 1 2 3...

Страница 318: ...eset value 0x0000_0000 Register offset 10078 11078 11178 11278 11378 11478 11578 11678 11778 11878 11978 11A78 11B78 11C78 11D78 11E78 11F78 Bits 0 1 2 3 4 5 6 7 00 07 BASE 08 15 Reserved 16 23 Reserv...

Страница 319: ...EN LARGE_ SYS Reserved 8 15 Reserved 16 23 MC_ID 15 8 24 31 MC_ID 7 0 Bits Name Description Type Reset Value 0 MC_EN Multicast can be disabled by setting this bit 0 Disabled 1 Enabled R W 0 1 LARGE_ S...

Страница 320: ...ent to all egress ports whose multicast select bit is set to 1 However the multicast packet is not sent to the port from which it was received regardless of the setting of that port s multicast select...

Страница 321: ...lue 0 1 Reserved N A R 0 2 SCRATCH Scratch Pad This bit controls no functionality It is a read write scratch pad bit for software use R W 0 3 4 Reserved N A R 0 5 FORCE_REINIT Force Link Re initializa...

Страница 322: ...0 14 LINK_INIT_NOTIF ICATION_EN Enables interrupts and port writes for LINK_INIT_NOTIFICATION events 0 Interrupt and or port write disabled 1 Interrupt and or port write enabled R W 0 15 LUT_PAR_ERR_...

Страница 323: ...pth Interrupt Enable An interrupt is generated when the OUTB_DEPTH bit is set in the RapidIO Port x Interrupt Status Register on page 328 R W 0 28 INB_DEPTH_EN Input Queue Depth Interrupt Enable An in...

Страница 324: ...only one outstanding request at a time Subsequent requests are ignored until the multicast control symbol is sent Register name SP 0 15 _SEND_MCS Reset value 0x0000_0002 Register offset 1300C 1310C 13...

Страница 325: ...Reserved PORT_NUM Bits Name Description Type Reset Value 0 7 DESTID_MSB Most significant byte of a 16 bit destination ID used in the lookup operation which caused the error Only valid if the LG_DESTID...

Страница 326: ...e LUT entry is mapped The PORT_NUM field value is the port to which the packet could be routed 0x0 to 0xF Caution The value of this bit is unpredictable when there is a parity error in the LUT For mor...

Страница 327: ...0 Encoding for control symbol This field uses the parameters PAR_0 and PAR_1 R W 0 3 7 PAR_0 Used in conjunction with stype0 encoding R W 0 8 12 PAR_1 Used in conjunction with stype0 encoding R W 0 13...

Страница 328: ...r This bit is cleared by writing a 1 to it or by clearing all bits in the RapidIO Port x Error Detect CSR on page 296 R W1C 0 14 LINK_INIT_ NOTIFICATION Link Initialization Notification Once set the L...

Страница 329: ...ge 57 Once set the bit remains unchanged until all the error sources are cleared The setting of this bit generates an interrupt if the IRQ_EN bit in RapidIO Port x Control Independent Register on page...

Страница 330: ...s set when Reordering Count reaches the maximum number defined in the Inbound Reordering Threshold field in the RapidIO Port x Reordering Counter Register on page 362 To get an interrupt in this statu...

Страница 331: ...Reserved 24 31 ILL_TRANS _GEN Reserved MAX_RET RY_GEN OUTB_DE PTH_GEN INB_DEPT H_GEN INB_RDR_ GEN Reserved TEA_GEN Bits Name Descriptiona Type Reset Value 0 12 Reserved N A R 0 13 MC_TEA_GEN Forces t...

Страница 332: ...as zero R W1S 0 30 Reserved Reserved R W1S 0 31 TEA_GEN Forces the TEA bit to be set to 1 This bit always reads as zero R W1S 0 a All bits in this register set clear bits in the RapidIO Port x Interr...

Страница 333: ...t to these registers Table 43 Tundra Specific Per Port Performance Registers Port Register Offset Description SP0 13000 1x 4x mode serial port SP1 13100 1x mode serial port SP2 13200 1x mode serial po...

Страница 334: ...rformance Statistics Counter 0 Register on page 346 and RapidIO Port x Performance Statistics Counter 1 Register on page 347 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setti...

Страница 335: ...Counter 0 Register on page 346 0 If all PS0_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 0 Register on page 346 is disabled 1 Count priority 1 packets R W 0 3 PS0_PRIO0...

Страница 336: ...lticast packet including header R W 0 16 PS1_PRIO3 Performance Stats Reg PS1 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated fo...

Страница 337: ...rved N A R 0 29 31 PS1_TYPE Performance Stats Reg PS1 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 1 R...

Страница 338: ...nter 2 Register on page 348 and RapidIO Port x Performance Statistics Counter 3 Register on page 349 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setting PSy_PRIO 0 3 to all o...

Страница 339: ...rol Register on page 342 0 If all PS2_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 342 is disabled 1 Count priority 1 packets R W 0 3 PS2...

Страница 340: ...tire multicast packet including header R W 0 16 PS3_PRIO3 Performance Stats Reg PS3 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumul...

Страница 341: ...rved N A R 0 29 31 PS3_TYPE Performance Stats Reg PS3 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 3 R...

Страница 342: ...Statistics Counter 4 Register on page 350 and RapidIO Port x Performance Statistics Counter 5 Register on page 351 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setting PSy_PR...

Страница 343: ...Counter 4 Register on page 350 0 If all PS4_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 Register on page 350 is disabled 1 Count priority 1 packets R W 0 3 PS4_PRIO0...

Страница 344: ...multicast packet including header R W 0 16 PS5_PRIO3 Performance Stats Reg PS5 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated...

Страница 345: ...5 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 5 Register on page 351 Retries are not counted as part...

Страница 346: ...lue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS0_CTR is enabled when PS0_PRIO 0 3 value in the RapidIO Port x P...

Страница 347: ...lue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS1_CTR is enabled when PS1_PRIO 0 3 value in the RapidIO Port x P...

Страница 348: ...ter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS2_CTR is enabled when PS2_PRIO 0 3 value in the RapidIO Po...

Страница 349: ...lue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS3_CTR is enabled when PS3_PRIO 0 3 value in the RapidIO Port x P...

Страница 350: ...is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS4_CTR is enabled when PS4_PRIO 0 3 value in the RapidIO Port x Perfo...

Страница 351: ...R counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS5_CTR is enabled when PS5_PRIO 0 3 value in the Rapi...

Страница 352: ...80 13880 13980 13A80 13B80 13C80 13D80 13E80 13F80 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPTH Reserved LEAK_RT 24 31 LEAK_RT Bits Name Description Type Reset Value 0 15 CONG_PE...

Страница 353: ...ill reaches or exceeds 3 7 the congestion counter increments when the buffer fill reaches 8 8 Reserved R W 0x0 20 Reserved N A R 0 21 31 LEAK_RT This value is the leak rate for both the receiver and t...

Страница 354: ...requency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 306 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable OUTB_DEPTH interrupt is generated Re...

Страница 355: ...CONG_THRESH Output Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the OUTB_DEPTH status bit in the RapidIO Port x Interr...

Страница 356: ...ding the CONG_PERIOD_CTR clears the counter value The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Transmitter Output Queue Depth Threshold Register is set to 0 Reg...

Страница 357: ...eset value 0x0000_0000 Register offset 13090 13190 13290 13390 13490 13590 13690 13790 13890 13990 13A90 13B90 13C90 13D90 13E90 13F90 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPT...

Страница 358: ...packets in the input queue meets or exceeds this number the congestion counter is incremented 0 Disables congestion monitoring 1 The congestion counter increments when the buffer fill reaches or exce...

Страница 359: ...frequency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 306 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable INB_DEPTH interrupt is generated R...

Страница 360: ...CONG_THRESH Input Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the INB_DEPTH status bit in the RapidIO Port x Interru...

Страница 361: ...G_PRIOD_CTR clears the register The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Receiver Input Queue Depth Threshold Register is set to 0 Register name SP 0 15 _RX...

Страница 362: ...8 Register name SP 0 15 _REORDER_CTR Reset value 0x0000_FFFF Register offset 130A0 131A0 132A0 133A0 134A0 135A0 136A0 137A0 138A0 139A0 13AA0 13BA0 13CA0 13DA0 13EA0 13FA0 Bits 0 1 2 3 4 5 6 7 00 7 C...

Страница 363: ...and some read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 143 for more information on the use of I2C controller register loading capability Software...

Страница 364: ...G_GBL register TX_EN in the SMACx_CFG_CH3 register TX_EN in the SMACx_CFG_CH2 register TX_EN in the SMACx_CFG_CH1 register TX_EN in the SMACx_CFG_CH0 register RX_PLL_PWRON in the SMACx_CFG_CH0 registe...

Страница 365: ...e Description Type Reset Value 0 HALF_RATE Baud Rate Control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED fi...

Страница 366: ...s Configuration Global on page 374 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge may be generated by writing a 0 and then a 1 to the regist...

Страница 367: ...Serial Port Electrical Layer Registers 367 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com 31 Reserved N A Note Only write 1 to this reserved field R W 1 Continued Bits Name D...

Страница 368: ...rved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divider setting selected by...

Страница 369: ...ation Global on page 374 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W...

Страница 370: ...1 0 RX_ALIGN _EN Reserved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divide...

Страница 371: ...PLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0...

Страница 372: ...served Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by...

Страница 373: ...nfiguration Global on page 374 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register b...

Страница 374: ...BYPASS_INIT is set to 1 R W 1 1 BYPASS_INI T Control bit to bypass initialization logic 0 default SerDes initialization is determined by SP_IO_SPEED 1 0 1 Bypass initialization logic set by the SP_IO...

Страница 375: ...K_O FF 0 Turns on the MPLL clock 1 Stops the reference clock This bit is read only unless BYPASS_INIT in is set to 1 R W 0 26 31 Reserved N A R W Undefined The reserved bits in this register are conne...

Страница 376: ...5 b10101 1133 1 22 0x16 5 b10110 1142 8 23 0x17 5 b10111 1152 5 24 0x18 5 b11000 1162 2 25 0x19 5 b11001 1171 9 26 0x1A 5 b11010 1181 6 27 0x1B 5 b11011 1191 3 28 0x1C 5 b11100 1200 9 29 0x1D 5 b11101...

Страница 377: ...www idt com 5 h07 521 133 5 h08 563 144 5 h09 605 155 5 h0A 648 165 5 h0B 692 176 5 h14 605 100 5 h15 670 111 5 h16 735 121 5 h17 800 133 5 h18 865 144 5 h19 932 155 5 h1A 997 165 5 h1B 1065 3176 Tabl...

Страница 378: ...egister offset 130C4 132C4 134C4 136C4 138C4 13AC4 13CC4 13EC4 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved MPLL_PRESCALE 1 0 Unused 16 23 Unused 24 31 Unused Reserved Bits Name Description Type...

Страница 379: ...to determine when a link is powered up and enabled but dead that is there is no link partner responding When a link is declared dead the transmitting port on the Tsi576 removes all packets from its t...

Страница 380: ...ation refer to Port Loopback Testing on page 79 R W 0 23 DLB_EVEN_ EN Digital Equipment Loopback Mode Even numbered Port Digital equipment loopback mode connects Tx data flow to Rx data flow before th...

Страница 381: ...ng to this register overrides the configuration provided by the pin 0 Normal mode of operation 1 Port powered down R W Undefined 29 PWDN_X4 Power down control for even numbered ports using this MAC In...

Страница 382: ...7 00 07 Reserved RDR_LIMIT 08 15 RDR_LIMIT _EN Reserved IN_ARB_MODE Reserved TEA_INT_E N TEA_EN 16 23 TEA_OUT 15 8 24 31 TEA_OUT 7 0 Bits Name Description Type Reset Value 0 3 Reserved N A R 0x0 4 7...

Страница 383: ...rupt is produced when a TEA event occurs R W 0 15 TEA_EN TEA Enable 0 TEA timer is disabled similar to writing all 0s to the TEA_OUT field 1 TEA timer is enabled R W 1 16 31 TEA_OUT 1 5 0 TEA Period T...

Страница 384: ...PORT9_IR Q PORT8_IR Q 24 31 PORT7_IR Q PORT6_IR Q PORT5_IR Q PORT4_IR Q PORT3_IR Q PORT2_IR Q PORT1_IR Q PORT0_IR Q Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 PORT15_IRQ Serial P...

Страница 385: ...Device Technology www idt com 26 PORT5_IRQ Serial port 5 IRQ R W1C 0 27 PORT4_IRQ Serial port 4 IRQ R W1C 0 28 PORT3_IRQ Serial port 3 IRQ R W1C 0 29 PORT2_IRQ Serial port 2 IRQ R W1C 0 30 PORT1_IRQ...

Страница 386: ...P8_ERR 24 31 P7_ERR P6_ERR P5_ERR P4_ERR P3_ERR P2_ERR P1_ERR P0_ERR Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 P15_ERR Port 15 violated the maximum multicast latency time and wi...

Страница 387: ...27 P4_ERR Port 4 violated the maximum multicast latency time and will not be multicast to R W1C 0 28 P3_ERR Port 3 violated the maximum multicast latency time and will not be multicast to R W1C 0 29...

Страница 388: ...00_0000 Register offset 1AA0C Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 P15_SET P14_SET P13_SET P12_SET P11_SET P10_SET P9_SET P8_SET 24 31 P7_SET P6_SET P5_SET P4_SET P3_SET P2_SET P1_...

Страница 389: ...once every time this bit is written as a 1 R W1S 0 27 P4_SET Port 4 multicast mask is overridden once every time this bit is written as a 1 R W1S 0 28 P3_SET Port 3 multicast mask is overridden once e...

Страница 390: ...ORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 Bits Name Description Type Reset Value 0 3 Reserved N A Note These upper 4 bits are reserved in order to be compatible with the I2C IP Refer to the I2C C...

Страница 391: ...R 0 21 PORT10 Port 10 Interrupt R 0 22 PORT9 Port 9 Interrupt R 0 23 PORT8 Port 8 Interrupt R 0 24 PORT7 Port 7 Interrupt R 0 25 PORT6 Port 6 Interrupt R 0 26 PORT5 Port 5 Interrupt R 0 27 PORT4 Port...

Страница 392: ...EN PORT5_EN PORT4_EN PORT3_EN PORT2_EN PORT1_EN PORT0_EN Bits Name Description Type Reset Value 0 3 Reserved N A R 0 4 RCS_EN Four Reset Control Symbols Interrupt Enable R W 0 5 MCS_EN Multicast Event...

Страница 393: ...Enable R W 0 25 PORT6_EN Port 6 Interrupt Enable R W 0 26 PORT5_EN Port 5 Interrupt Enable R W 0 27 PORT4_EN Port 4 Interrupt Enable R W 0 28 PORT3_EN Port 3 Interrupt Enable R W 0 29 PORT2_EN Port 2...

Страница 394: ...C14 Bits 0 1 2 3 4 5 6 7 00 07 PW_TIMER Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 3 PW_TIMER Port write Timer This field defines the time period to...

Страница 395: ...port write is sent any remaining port write requests from any port sets a bit in the register Register name RIO_PW_OREQ_STATUS Reset value 0x0000_0000 Register offset 1AC18 Bits 0 1 2 3 4 5 6 7 00 07...

Страница 396: ...erved MCES_CTRL Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 3 MCES_CTRL MCES Pin Control 00 Disabled The MCES pin does not affec...

Страница 397: ...ion of the IDT specific registers that is supported by this device Register name RIO 0 15 _MC_REG_VER Reset value 0x0000_0001 Register offset 1B000 1B100 1B200 1B300 1B400 1B500 1B600 1B700 1B800 1B90...

Страница 398: ...0 Do not remove port from multicast operations if the multicast maximum latency timer expires for this port 1 Remove this port from future multicast operations if the multicast maximum latency timer...

Страница 399: ...packets are accepted if the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either greater than or equal t...

Страница 400: ...1B910 1BA10 1BB10 1BC10 1BD10 1BE10 1BF10 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved...

Страница 401: ...B14 1BC14 1BD14 1BE14 1BF14 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_...

Страница 402: ...B18 1BC18 1BD18 1BE18 1BF18 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_...

Страница 403: ...B1C 1BC1C 1BD1C 1BE1C 1BF1C Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_...

Страница 404: ...s The SerDes is fully initialized when MPLL_PWR_ON is equal to 1 see SRIO MAC x SerDes Configuration Global on page 374 The SerDes register offsets in this section are based on lane 0 In order to defi...

Страница 405: ...eserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bi...

Страница 406: ...eserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bi...

Страница 407: ...eserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bi...

Страница 408: ...eserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bi...

Страница 409: ...ignal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error c...

Страница 410: ...and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COU...

Страница 411: ...and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COU...

Страница 412: ...and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COU...

Страница 413: ...e reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the usefu...

Страница 414: ...e reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the usefu...

Страница 415: ...e reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the usefu...

Страница 416: ...e reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the usefu...

Страница 417: ...ange within a consecutive 256 byte address space For peripheral addresses the lowest address maps to the least significant byte of the internal register LSB while the highest address maps to the most...

Страница 418: ...I2C Internal Read Data Register 0x1D218 0x1D21C 0x18 0x1F Reserved 0x1D220 0x20 0x23 EXI2C_ACC_STAT Externally Visible I2 C Slave Access Status Register 0x1D224 0x24 0x27 EXI2C_ACC_CNTRL Externally V...

Страница 419: ...SD Setup and Hold Timing Register 0x1D34C n a I2C_SCL_PERIOD I2C_SCLK High and Low Timing Register 0x1D350 n a I2C_SCL_MIN_PERIOD I2C_SCLK Minimum High and Low Timing Register 0x1D354 n a I2C_SCL_ARB_...

Страница 420: ...a chip reset 13 2 1 I2 C Device ID Register This register identifies the version of the IDT I2C block in this device Register name I2C_DEVID Reset value 0x0000_0001 Register offset 0x1D100 Bits 0 1 2...

Страница 421: ...to be unaffected by this reset Register name I2C_RESET Reset value 0x0000_0000 Register offset 0x1D104 Bits 0 1 2 3 4 5 6 7 00 07 SRESET Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Nam...

Страница 422: ...rocessed from MSB to LSB within an I2 C transaction 1 Data from to data registers is ordered processed from LSB to MSB within an I2 C transaction Data registers are I2 C Master Transmit Data Register...

Страница 423: ...rs Register Descriptions 423 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com Do not change this register while a master operation is active The effect on the transaction cannot...

Страница 424: ...NTRL Reset value 0x0000_0000 Register offset 0x1D10C Bits 0 1 2 3 4 5 6 7 00 07 START WRITE Reserved SIZE 08 15 Reserved 16 23 PADDR 24 31 PADDR Bits Name Description Type Reset Value 00 START Start O...

Страница 425: ...e of 000 should not be normally used for a Read operation as any device put into read mode assumes at least one byte will be read An exception would be the SMBus Quick Command protocol to a device tha...

Страница 426: ...it for ACK If PA_SIZE is 00 or 11 this phase is skipped Any loss of arbitration will abort with MCOL Any NACK will abort with MNACK 4 Send Data WRITE 1 If SIZE 0 send SIZE bytes from I2C_MST_TDATA bas...

Страница 427: ...RDER is 1 bytes are loaded from LSB to MSB in order RBYTE0 RBYTE1 RBYTE2 RBYTE3 If the transaction size is less than four 4 bytes that is SIZE in the I2C Master Control Register 4 then any remaining b...

Страница 428: ...DER is 1 bytes are taken from LSB to MSB in order TBYTE0 TBYTE1 TBYTE2 TBYTE3 If the transaction size is less than 4 bytes that is SIZE in the I2 C Master Control Register 4 then any remaining bytes i...

Страница 429: ...TES Bits Name Description Type Reset Value 00 SLV_ACTIVE Slave Active 0 Slave is not addressed 1 Slave is addressed by external master and a read or write is active on the bus This bit is set followin...

Страница 430: ...ster 11 Data outgoing read by external master At the end of a slave operation this field will hold its value until the next START RESTART If a slave operation aborts this field will qualify where in t...

Страница 431: ...rts this field will qualify where in the transaction the error occurred R 000 23 MST_AN Master Ack Nack 0 Master transaction is not in the ACK NACK bit of a byte 1 Master transaction is in the ACK NAC...

Страница 432: ...t Register is de asserted Register name I2C_INT_STAT Reset value 0x0000_0000 Register offset 0x1D11C Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved...

Страница 433: ...by an external master invoking a write to an internal register This will not assert if slave writes are disabled WR_EN in the I2 C Slave Configuration Register 0 R W1C 0 22 SA_READ Slave Read 0 Inter...

Страница 434: ...W1C 0 29 MA_NACK Master NACK 0 Interrupt status not asserted 1 NACK received during transaction A transaction initiated through the I2 C Master Control Register aborted due to receipt of a NACK in res...

Страница 435: ...erved BL_FAIL BL_OK 16 23 Reserved SA_ FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved MA_COL MA_TMO MA_NACK MA_ATMO MA_OK Bits Name Description Type Reset Value 0 5 Reserved Reserved R 0x00 6 OMB...

Страница 436: ...nable MA_DIAG Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 25 26 Reserved Reserved R 00 27 MA_COL Enable MA_COL Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 28 MA_T...

Страница 437: ...t value 0x0000_0000 Register offset 0x1D124 Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_ FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved SA_FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved...

Страница 438: ...s set R W1S 0 24 MA_DIAG Set MA_DIAG Interrupt 0 No effect 1 Interrupt is set R W1S 0 25 26 Reserved Reserved R 00 27 MA_COL Set MA_COL Interrupt 0 No effect 1 Interrupt is set R W1S 0 28 MA_TMO Set M...

Страница 439: ...effect 0 Transactions that read the Externally Visible I2 C Internal Read Data Register on page 449 will not invoke reads of the internal registers 1 Transactions that read the Externally Visible I2 C...

Страница 440: ...erface is enabled SLV_ADDR is responded to when transaction started by external master When enabled the slave interface will acknowledge transactions to the SLV_ADDR from an external master If not ena...

Страница 441: ...latched at power up from the state of input pins This allows board configuration of up to four unique Tsi576 devices on the I2C bus These two bits are then locked for writing until the SLV_UNLK bit is...

Страница 442: ...is register can be read and written after boot loading is complete but has no further effect on block operation Register name I2C_BOOT_CNTRL Reset value Undefined Register offset 0x1D140 Bits 0 1 2 3...

Страница 443: ...ddress as a 256 byte page select typically 2K EEPROMs When enabled and the 1 byte peripheral address wraps back to zero the least significant 3 bits of the device address is incremented followed by a...

Страница 444: ...eld R W Undefined 16 18 PAGE_MODE Page Mode 000 8 bytes 001 32 bytes 010 64 bytes 011 128 bytes 100 256 bytes 101 512 bytes 110 1024 bytes 111 Infinite This field modifies the boot load process to adj...

Страница 445: ...al address this field is shifted left by 3 and then copied internally upon boot start or a chain operation The internal address is then incremented as the boot load progresses For 2 byte addressing th...

Страница 446: ...end of the boot load process this register will contain the last register address read from the EEPROM or the first four bytes of the register count Register name EXI2C_REG_WADDR Reset value 0x0000_0...

Страница 447: ...31 WDATA Bits Name Description Type Reset Value 0 31 WDATA Internal Register Write Data Data written by the external I2C master to be used for an internal register write When WSIZE is configured for 4...

Страница 448: ...Register name EXI2C_REG_RADDR Reset value 0x0000_0000 Register offset 0x1D210 Bits 0 1 2 3 4 5 6 7 00 07 ADDR 08 15 ADDR 16 23 ADDR 24 31 ADDR Reserved Bits Name Description Type Reset Value 0 29 ADDR...

Страница 449: ...ding this register When RSIZE is configured for 4 byte access in the Externally Visible I2 C Internal Access Control Register on page 452 this register is updated by the read of an internal register w...

Страница 450: ...3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 ACC_OK Reserved OMB_ FLAG IMB_ FLAG Reserved ALERT_ FLAG Bits Name Description Type Reset Value 00 23 Reserved Reserved R 0x00_0000 24 ACC_...

Страница 451: ...x This bit is set when data is written to the incoming mailbox register Externally Visible I2C Incoming Mailbox Register by an external I2C master This bit remains set flag up until software reads the...

Страница 452: ...lave interface This register corresponds to the I2 C peripheral addresses 0x24 through 0x27 Register name EXI2C_ACC_CNTRL Reset value 0x0000_00A0 Register offset 0x1D224 Bits 0 1 2 3 4 5 6 7 00 07 Res...

Страница 453: ...ng is on consecutive internal registers can be read in one I2C transaction without the need to reset the peripheral address because the peripheral address wraps from 0x17 back to 0x14 If auto incremen...

Страница 454: ...occurs the bit remains set The software status bits 1 3 are R W from the register bus They can be set or cleared by software and thereby used for any system purpose An external I2 C master can write...

Страница 455: ...ing mailbox not filled since last clear 1 Outgoing mailbox is filled This bit asserted indicates that software has written to the outgoing mailbox since this bit was last cleared R 0 5 IMBR Incoming M...

Страница 456: ...port could not be sent in the required time R 0 15 MCE Multicast Work Queue Dropped Packet Interrupt 0 No interrupt 1 Multicast logic dropped a packet R 0 16 PORT15 Port 15 Interrupt 0 No interrupt 1...

Страница 457: ...d an interrupt to the processor R 0 26 PORT5 Port 5 Interrupt 0 No interrupt 1 Port 5 has asserted an interrupt to the processor R 0 27 PORT4 Port 4 Interrupt 0 No interrupt 1 Port 4 has asserted an i...

Страница 458: ...0x87 Register name EXI2C_STAT_ENABLE Reset value 0xFFFF_FFFF Register offset 0x1D284 Bits 0 1 2 3 4 5 6 7 00 07 RESET SW_ STAT2 SW_ STAT1 SW_ STAT0 OMBW IMBR I2C TEA 08 15 RCS MCS Reserved LOGICAL MC_...

Страница 459: ...rved Reserved These bits are unused in the Tsi576 The enables can be changed but have no effect R W 111 13 LOGICAL Enable LOGICAL Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1...

Страница 460: ...ERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 24 PORT7 Enable PORT7 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FL...

Страница 461: ...ble PORT1 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 31 PORT0 Enable PORT0 Alert Response 0 Status asserted will not ena...

Страница 462: ...1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 DATA 24 31 DATA Bits Name Description Type Reset Value 0 31 DATA Mailbox data to be transferred to an external I2 C master Every write to this register by sof...

Страница 463: ...s register corresponds to the I2 C peripheral addresses 0x94 through 0x97 Register name EXI2C_MBOX_IN Reset value 0x0000_0000 Register offset 0x1D294 Bits 0 1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 D...

Страница 464: ...corresponding bits in the I2C Enable Event Register and then determine whether a related bit in the I2C_INT_STAT register is set Note These registers are affected by a reset controlled by the I2 C Res...

Страница 465: ...ing mailbox R W1C 0 09 OMBR Outgoing Mailbox Read Event 0 Event not asserted 1 Slave interface completed a read transaction to the outgoing mailbox when the OMB_FLAG was set The event is asserted only...

Страница 466: ...d Error Event 0 Event not asserted 1 The boot load sequence failed due to an error during register reading a protocol error NACK when ACK expected an I2C_SCLK low timer collision after the device addr...

Страница 467: ...me slave device This event can also assert during boot load and provides more information on the source of a BLERR event R W1C 0 28 MTRTO Master Transaction Timeout Event 0 Event not asserted 1 Transa...

Страница 468: ...SRESET is asserted in the I2C Reset Register Register name I2C_NEW_EVENT Reset value 0x0000_0000 Register offset 0x1D308 Bits 0 1 2 3 4 5 6 7 00 07 Reserved SDW SDR SD Reserved DTIMER DHIST DCMDD 08 1...

Страница 469: ...not asserted 1 Event asserted R W1S 0 12 STRTO Slave Transaction Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 13 SBTTO Slave Byte Timeout Event 0 Event not asserted 1 Event asserted R W...

Страница 470: ...ed R 00 26 MNACK Master NACK Received Event 0 Event not asserted 1 Event asserted R W1S 0 27 MCOL Master Collision Detect Event 0 Event not asserted 1 Event asserted R W1S 0 28 MTRTO Master Transactio...

Страница 471: ...MARBTO Bits Name Description Type Reset Value 00 Reserved Reserved R 0 01 SDW Slave Internal Register Write Done Enable 0 Event does not assert to interrupt status 1 Event will assert in interrupt st...

Страница 472: ...O Slave Byte Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 14 SSCLTO Slave I2C_SCLK Low Timeout Enable 0 Event does not assert to interru...

Страница 473: ...27 MCOL Master Collision Detect Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 28 MTRTO Master Transaction Timeout Enable 0 Event does not assert...

Страница 474: ...ype Reset Value 00 03 Reserved Reserved R 0x0 04 15 USDIV Period Divider for Micro Second Based Timers This field divides the reference clock down for use by the Idle Detect Timer the Byte Timeout Tim...

Страница 475: ...07 START_SETUP 08 15 START_SETUP 16 23 START_HOLD 24 31 START_HOLD Bits Name Description Type Reset Value 00 15 START_SETUP Count for the START Condition Setup Period Defines the minimum setup time fo...

Страница 476: ...STOP Condition Setup Period Defines the minimum setup time for the STOP condition that is both I2C_SCLK seen high and I2C_SD seen low prior to I2C_SD released high This is a master only timing paramet...

Страница 477: ...I2C_SD Setup Period Defines the minimum setup time for the I2C_SD signal that is I2C_SD set to desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface Note This...

Страница 478: ...SCL_LOW 24 31 SCL_LOW Bits Name Description Type Reset Value 00 15 SCL_HIGH Count for I2C_SCLK High Period Defines the nominal high period of the clock from rising edge to falling edge of I2C_SCLK Th...

Страница 479: ...INL 24 31 SCL_MINL Bits Name Description Type Reset Value 00 15 SCL_MINH Count for I2C_SCLK High Minimum Period Defines the minimum high period of the clock from rising edge seen high to falling edge...

Страница 480: ...from I2C_SCLK falling edge to the next I2C_SCLK rising edge Value 0x0 disables the timeout Period SCL_TO SCL_TO Period USDIV where USDIV is the microsecond time defined in the I2C Time Period Divider...

Страница 481: ...mount of time for a byte to be transferred on the I2C bus This covers the period from Start condition to next ACK NACK between two successive ACK NACK bits or from ACK NACK to Stop Restart condition A...

Страница 482: ...r Initial reset value is used for overall boot load timeout During normal operation this timer can be used for any general purpose timing A value of 0 disables the timeout Period DTIMER COUNT Period M...

Страница 483: ...ence This register is initialized to the count read from the first two bytes of the EEPROM after reset or to the first two byte read after a boot chaining operation The field counts down as each regis...

Страница 484: ...Disabled 0 Boot enabled 1 Boot disabled R Undefined 02 PASIZE Peripheral Address Size 0 1 byte peripheral address 1 2 byte peripheral address Note This is the state of the I2C_BOOT_CNTRL PSIZE field...

Страница 485: ...n the Logical Common Transport and Physical Layer specifications TheTsi576 fully manages the end to end link on each port A 1 Protocol The RapidIO Physical Layer 1x 4x LP Serial specification defines...

Страница 486: ...for the 1x and 4x interfaces and defines the link initialization sequence for clock synchronization The PCS function is also responsible for idle sequence generation encoding for transmission and lane...

Страница 487: ...Code Group Use Number of Groups Encoding 8 bit Value PD packet delimiter 1 K28 3 0x7C SC start of Control Symbol 1 K28 0 0x1C I 1x Idle K or R or A see below 0xBC or 0xFD or 0xFB K 1x Sync 1 K28 5 0xB...

Страница 488: ...5 bits stype0 0 2 definition P 0 P 1 stype1 0 2 cmd CRC 000 pkt accepte d pkt ackID buf_status 001 pkt rtry pkt ackID buf_status 010 pkt not acce pted pkt ackID cause see below 011 reserved 100 statu...

Страница 489: ...0110 011 11 reserved 10000 OK 10001 111 11 reserved stype1 stype1 0 2 definition cmd 0 2 cmd function pkt delimiter 000 start of pkt 000 reserved yes 001 stomp 000 reserved yes 010 end of pkt 000 rese...

Страница 490: ...A Serial RapidIO Protocol Overview Physical Layer 490 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 491: ...t are outside of the RapidIO specification The ability to support multiple line rates gives the Tsi576 flexibility in both application support and power consumption Table 53 shows the supported line r...

Страница 492: ...the recommended method B 1 1 1 Modification by EEPROM Boot Load Modifying the EEPROM is the recommended method for using the S_CLK at 125 MHz to create a 3 125 Gbps link baud rate because the EEPROM b...

Страница 493: ...ed in Example Maintenance Transaction Sequence on page 493 Example Maintenance Transaction Sequence The following procedure configures port two After these steps are complete port two can train with i...

Страница 494: ...MACx_CFG_GBL register Write offset 0x132C0 with 0x4A060005 Write offset 0x132c0 with 0xCA060005 11 Set the MPLL_PWRON bit in the SMACx_CFG_GLOBAL register Write offset 0x132C0 with 0xCA060085 Ensure t...

Страница 495: ...onnect Specification Revision 1 3 B 2 1 1 Port Link Time out CSR RapidIO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 6 6 2 2 Port Link Time out CSR Block Offset 0x20 The R...

Страница 496: ...IMER_EN to be de asserted When the state machine is not in the SILENT state SILENCE_TIMER_DONE is de asserted IDT Implementation The Tsi576 s silence timer does not have user programmable registers Th...

Страница 497: ...e and if the link partner supports 4x mode for all four lanes to be aligned The DISCOVERY_TIMER has a default value of 9 decimal but can be programmed to various values The results of changing the DIS...

Страница 498: ...llowing formula 2 13 DLT_THRESH P_CLK period P_CLK is 100 MHz which gives a P_CLK period of 10nS Default value of DLT_THRESH is 0x7FFF which corresponds to 32767 Using these parameters the populated f...

Страница 499: ...r use by the Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider Period USDIV Period P_CLK USDIV 1 P_CLK is 10 ns Tsi576 reset value is 0x0063 M...

Страница 500: ...ng for the Stop condition when generated by the master control logic and the Idle Detect timer The Stop Idle register is broken down as follows The timer period for the STOP_SETUP is relative to the r...

Страница 501: ...ace It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SDA_SETUP Count for the I2C_SD Setup Period The SDA_SE...

Страница 502: ...OW field defines the nominal low period of the clock from falling edge to rising edge of I2C_SCLK This is a master only parameter The actual observed period may be longer if other devices pull the clo...

Страница 503: ...e maximum amount of time for a slave device holding the I2C_SCLK signal low This timeout covers the period from I2C_SCLK falling edge to the next I2C_SCLK rising edge A value of 0 disables the timeout...

Страница 504: ...is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus This covers the period from Start to Stop A value of 0 dis...

Страница 505: ...ers reside is a synchronous bus clocked by the P_CLK source A decrease in the P_CLK frequency causes a proportional increase in register access time during RapidIO maintenance transactions JTAG regist...

Страница 506: ...B Clocking P_CLK Programming 506 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 507: ...ad_prbs_all txt Script C 1 Tsi576_start_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern generator for each lane to be tested The SerDes in a port are offset by 0x40 from the l...

Страница 508: ...0000002 w 1e6e0 00000002 Port 8 w 1e820 00000002 Start 2 7 Pattern Generator w 1e860 00000002 w 1e8a0 00000002 w 1e8e0 00000002 Port a w 1ea20 00000002 Start 2 7 Pattern Generator w 1ea60 00000002 w 1...

Страница 509: ...1 25 Gbps PRBS testing at 2 5 or 3 125 Gbps requires the HALF_RATE bit to be cleared The data to be written therefore becomes 0x203CE511 i 0 Port 0 w 130b0 A03CE511 Clear RX_ALIGN_EN w 130b4 A03CE511...

Страница 510: ...11 w 13eb8 A03CE511 w 13ebc A03CE511 C 3 Tsi576_sync_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern matcher for each lane to be tested The SerDes in a port are offset by 0x40...

Страница 511: ...b0 0000000a w 1e2f0 0000000a w 1e230 00000002 w 1e270 00000002 w 1e2b0 00000002 w 1e2f0 00000002 Port 4 w 1e430 0000000a Sync pattern matcher w 1e470 0000000a w 1e4b0 0000000a w 1e4f0 0000000a w 1e430...

Страница 512: ...00002 w 1e870 00000002 w 1e8b0 00000002 w 1e8f0 00000002 Port a w 1ea30 0000000a Sync pattern matcher w 1ea70 0000000a w 1eab0 0000000a w 1eaf0 0000000a w 1ea30 00000002 w 1ea70 00000002 w 1eab0 00000...

Страница 513: ...Tsi576_read_prbs_all txt Script This script is used to read the PRBS values Note that the PRBS error counter and overflow bit fields must be read twice to determine the correct value The result of the...

Страница 514: ...e 6 2016 Integrated Device Technology www idt com Port4 r 1e430 r 1e430 r 1e470 r 1e470 r 1e4b0 r 1e4b0 r 1e4f0 r 1e4f0 Port6 r 1e630 r 1e630 r 1e670 r 1e670 r 1e6b0 r 1e6b0 r 1e6f0 r 1e6f0 Port8 r 1e...

Страница 515: ...ser Manual June 6 2016 Integrated Device Technology www idt com r 1ea30 r 1ea70 r 1ea70 r 1eab0 r 1eab0 r 1eaf0 r 1eaf0 Portc r 1ec30 r 1ec30 r 1ec70 r 1ec70 r 1ecb0 r 1ecb0 r 1ecf0 r 1ecf0 Porte r 1e...

Страница 516: ...C PRBS Scripts Tsi576_read_prbs_all txt Script 516 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 517: ...tion shows the EEPROM script used in Modification by EEPROM Boot Load D 1 Script ew 0 0047FFFF ew 4 FFFFFFFF 1 ew 8 138c8 ew c 7FFF0012 2 ew 10 138c0 ew 14 CA060084 3 ew 18 138B0 ew 1c 203CA513 4 ew 2...

Страница 518: ...com 8 ew 40 138B4 ew 44 203C2513 9 ew 48 138B8 ew 4c 203C2513 A ew 50 138BC ew 54 203C2513 B ew 58 138B0 ew 5c 200C2513 C ew 60 138B4 ew 64 200C2513 D ew 68 138B8 ew 6c 200C2513 E ew 70 138BC ew 74 20...

Страница 519: ...12 ew 90 138c0 ew 94 CA060045 13 ew 98 138c0 ew 9c CA060005 14 ew a0 138c0 ew a4 4A060005 15 ew a8 138c0 ew ac CA060005 16 ew b0 138c0 ew b4 CA060085 17 ew b8 138B0 ew bc 203C2513 18 ew c0 138B4 ew c4...

Страница 520: ...203CA513 1D ew e8 138B8 ew ec 203CA513 1E ew f0 138BC ew f4 203CA513 1F ew f8 138B0 ew fc 203CE513 20 ew 100 138B4 ew 104 203CE513 21 ew 108 138B8 ew 10c 203CE513 22 ew 110 138BC ew 114 203CE513 23 ew...

Страница 521: ...136B0 ew 134 203CA513 27 ew 138 136B4 ew 13c 203CA513 28 ew 140 136B8 ew 144 203CA513 29 ew 148 136BC ew 14c 203CA513 2a ew 150 136B0 ew 154 203C2513 2b ew 158 136B4 ew 15c 203C2513 2c ew 160 136B8 ew...

Страница 522: ...136B8 ew 184 200C2513 31 ew 188 136BC ew 18c 200C2513 32 ew 190 136c0 ew 194 CA060004 33 ew 198 136c0 ew 19c CA060044 34 ew 1a0 136C4 ew 1a4 002C0545 35 ew 1a8 136c0 ew 1ac CA060045 36 ew 1b0 136c0 ew...

Страница 523: ...136B0 ew 1d4 203C2513 3b ew 1d8 136B4 ew 1dc 203C2513 3c ew 1e0 136B8 ew 1e4 203C2513 3d ew 1e8 136BC ew 1ec 203C2513 3e ew 1f0 136B0 ew 1f4 203CA513 3f ew 1f8 136B4 ew 1fc 203CA513 40 ew 200 136B8 ew...

Страница 524: ...ipts Script 524 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com 44 ew 220 136B8 ew 224 203CE513 45 ew 228 136BC ew 22c 203CE513 46 ew 230 136c8 ew 234 7FFF0002 47 ew 238 8 ew 2...

Страница 525: ...mable Driver Current and Equalization 77 Error Management 57 Error Management of Multicast Packets 120 Multicast Maximum Latency Timer 120 Silent Discard of Packets 121 Event Notification 123 Interrup...

Страница 526: ...MA Layer 486 Port Aggregation 4x and 1x link modes 68 1x 1x Configuration 69 4x 0x Configuration 70 Port Power up and Power down 216 Port Reset 122 Port Width Override 216 Port Write Notifications 135...

Страница 527: ...ntroller 228 Multicast 226 Power Supplies 229 Serial Port Configuration 222 Serial Port Lane Ordering Select 225 Serial Port Receive 221 Serial Port Speed Select 224 Serial Port Transmit 221 Signal Ty...

Страница 528: ...Index 528 Tsi576 User Manual June 6 2016 Integrated Device Technology www idt com...

Страница 529: ...June 6 2016 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose CA 95138 for SALES 800 345 7015 or 408 284 8200 www idt com for Tech Support srio idt com...

Страница 530: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...

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