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3. Serial RapidIO Electrical Interface > Port Power Down 74
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
3.5.3 Power-Down Options
The following power-down options are available on a port:
• A port’s main logic can be powered down at boot up through the SP{n}_PWRDN pins.
• The default configuration provided by the pins can be changed using the PWDN_X4 and
PWDN_X1 bits in the
“SRIO MAC x Digital Loopback and Clock Selection Register” . This can
occur during a boot load using an EEPROM on the I
2
C bus, or during normal operation through a
register write.
3.5.4 Configuration and Operation Through Power-down
The transceivers for the individual bit lanes can be powered down when they are not used. All valid
power-down scenarios are shown in
Table 6 .
Table 6: Serial Port Power-down Procedure
Mode for
Serial
Port n
Mode for
Serial
Port n+1 Required Power Down Configuration
4x N/A • De-assert the SP n _PWRDN pin and/or set the PWDN_X4 bit to 0 in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on page 379 .
• To save power, assert the SP n+1 _PWRDN pin and/or set the PWDN_X1 bit to 1 in the “SRIO
MAC x Digital Loopback and Clock Selection Register” on page 379 . If this bit is not set,
Port n+1 consumes unnecessary power.
1x 1x • De-assert the SP n _PWRDN pin and/or set the PWDN_X4 bit to 0 in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on page 379 .
• De-assert the SP n+1 _PWRDN pin and/or set the PWDN_X1 bit to 0 in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on page 379 .
1x Port Not
Used
• De-assert the SP n _PWRDN pin and/or set the PWDN_X4 bit to 0 in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on page 379 .
• To conserve power, assert the SP n+1 _PWRDN pin and/or set the PWDN_X1 bit to 1 in the
“SRIO MAC x Digital Loopback and Clock Selection Register” on page 379 . Otherwise, Port
n+1 consumes power unnecessarily.
Port Not
Used
1x • Not supported
Port Not
Used
Port Not
Used
• To save power, assert the SP n _PWRDN pin and/or set the PWDN_X4 bit to 1 in the “SRIO
MAC x Digital Loopback and Clock Selection Register” on page 379 .
• To conserve power, assert the SP n+1 _PWRDN pin and/or set the PWDN_X1 bit to 1 in the
“SRIO MAC x Digital Loopback and Clock Selection Register” on page 379 .