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Specifications A-1
A
Specifications
VXIbus General Information
Module Form
Single slot VXIbus C-size module
Connectors P1,
P2
Protocol
A16/A24/D16 Slave, Message-Based
VXIbus Revision
1.4
SCPI Revision
1993.0
Logical Address Settings
1 - 255, configured via DIP switches
Interrupt Level Settings
1 - 7, configured dynamically (no DIP switch)
Shared Memory
A24, D16, 64K points. Expandable to 512K points
Note: 1 point = 2 bytes, shared memory is the same as
waveform memory.
Synthesizer Reference Sources/Sample Clock
Reference Sources
External Reference Input from:
VXIbus CLK10
Optional Internal Reference:
PCB layout to provide for either internal
(1)
10 MHz TCXO with 1 ppm accuracy or
(2)
10 MHz Crystal with 100 ppm accuracy
Sample Clock
External Clock Input from:
(1)
Front Panel BNC, Frequency to 100 MHz, ECL compatible
(2) ECLTRG0, Synchronous Protocol, ECLTRG trigger
acceptor requirements with regard to pulse width and
frequency are waived.
External Clock Output to:
ECLTRG0, Synchronous Protocol, VXIbus ECLTRG trigger
source requirements with regard to pulse width and frequency
are waived.
Содержание 3152
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