UMTS/HSPA+ Module Series
UG89 Hardware Design
UG89_Hardware_Design 20 / 73
V
IH
min=1.2V
V
IH
max=2.0V
open.
DBG_CTS
33
DO Debug clear to send
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
If unused, keep it
open.
RF Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
ANT_MAIN
63
IO
Main antenna
50
Ω impedance
ADC Interface
Pin Name
Pin No
I/O
Description
DC Characteristics
Comment
ADC
6
AI
General purpose
analog to digital
converter interface
Voltage range:
0V to 1.2
If unused, keep it
open.
PCM Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
PCM_DIN
26
DI
PCM data input
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
If unused, keep it
open.
PCM_DOUT
24
DO PCM data output
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
If unused, keep it
open.
PCM_SYNC
25
IO
PCM data frame
synchronization
signal
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
In master mode, it
serves as an output
signal.
In slave mode, it
serves as an input
signal.
If unused, keep it
open.
PCM_CLK
27
IO
PCM data bit clock
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
In master mode, it
serves as an output
signal.
In slave mode, it
serves as an input
signal.
If unused, it is
recommended to
mount a 33pF