UMTS/HSPA+ Module Series
UG89 Hardware Design
UG89_Hardware_Design 33 / 73
Table 12: Pin Definition of the Debug UART Interface
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
The module provides a 1.8V UART interface. A level translator should be used if the application is equipped
with a 3.3V UART interface. A level translator TXS0108EPWR provided by
Texas Instruments
is
recommended. The following figure shows a reference design.
UART1_CTS
11
DO
DTE clear to send
UART1_RTS
14
DI
DTE request to send
UART1_DTR
46
DI
Data terminal ready
UART1_TXD
10
DO
Transmit data
UART1_RXD
12
DI
Receive data
UART1_DSR
44
DO
Data set ready
Pin Name
Pin No.
I/O
Description
Comment
DBG_RXD
30
DI
Debug receive data
1.8V power domain.
DBG_TXD
31
DO
Debug transmit data
DBG_RTS
32
DI
Debug request to send
DBG_CTS
33
DO
Debug clear to send
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0
0.45
V
V
OH
1.35
1.8
V
