UMTS/HSPA+ Module Series
UG89 Hardware Design
UG89_Hardware_Design 40 / 73
P CM _CLK
P CM _S YNC
P CM _DOUT
MS B
LS B
MS B
125us
1
2
2 5 6
2 5 5
P CM _DIN
MS B
LS B
MS B
Figure 18: Primary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 18: Pin Definition of PCM and I2C Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCM_DIN
26
DI
PCM data input
1.8V power domain
If unused, keep it open
PCM_DOUT
24
DO
PCM data output
1.8V power domain
If unused, keep it open
PCM_SYNC
25
IO
PCM data frame
synchronization
1.8V power domain .
In master mode, it serves as an
output signal.
In slave mode, it is used as an
input signal.
If unused, keep it open.
PCM_CLK
27
IO
PCM clock
1.8V power domain
In master mode, it serves as an
output signal.
In slave mode, it is used as an
input signal.
If unused, it is recommended to
mount a 33pF capacitor close to
the pin.
I2C_SCL
29
OD
I2C serial clock for an
An external 1.8V pull-up resistor