UMTS/HSPA+ Module Series
UG89 Hardware Design
UG89_Hardware_Design 41 / 73
Clock and mode can be configured by AT command, and the default configuration is short frame
synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC.
The following figure shows a reference design of a PCM interface with external codec IC.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8V
4
.7
K
4
.7
K
BCLK
LRCK
DAC
ADC
SCL
SDA
B
IA
S
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
Figure 19: Reference Circuit of PCM Application with Audio Codec
It is recommended to reserve an RC (R=22
Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
3.12. STATUS
The STATUS pin is an open drain output for the
module’s operation status indication. It can be connected
to a GPIO of DTE with a pulled-up resistor, or as an LED indication circuit as below. When the module is
turned on normally, the STATUS will present the low state. Otherwise, the STATUS will present high-
impedance state.
Table 19: Pin Definition of STATUS
external codec
is required.
If unused, it is recommended to
mount a 33pF capacitor close to
the pin.
I2C_SDA
28
OD
I2C serial data for an external
codec
An external 1.8V pull-up resistor
is required.
If unused, keep it open.
NOTE