PT AMC131, Руководство по оборудованию

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Functional Blocks
27
PCI Express
The PCI Express (PCIe) port is compatible with the PCI Express Base Specification Revision
1.0a and supports the following, with each lane at 2.5 Gbaud (2.0 Gb/s) only:
• x1, x2, x4, or x8 lane widths (build option 1)
• x1, x2 or x4 (build option 4)
The maximum supported packet payload size is 256 bytes. The interface supports virtual
channel 0 (VC0) and traffic class 0 (TC0) only. The PCIe interface can be configured by the
user as a PCIe Endpoint or as a Root Complex. PCIe is configured as an endpoint by default.
Enabling the PCIe port is also configurable. The PCIe lanes are routed to the AMC fat pipe
ports as shown in
Table 2-4, “SERDES Port Mapping,” below.
For more information about configuring PCIe, see “SW2 (PCI Express/SRIO Configurations),”
on page 39 and “Register 13,” on page 93 .
Note: Build option 2 was not implemented and is reserved.
Serial Rapid IO
The Serial Rapid IO (SRIO) port is compatible with the Serial Rapid IO Specification, Revision
1.0. It supports x1, or x4 lane widths with each lane at 3.125 Gbaud (2.5 Gb/s) only. The SRIO
interface can be configured by the user as an SRIO Agent or as a Host. SRIO is configured as
an Agent by default. It can also be configured with either small system 8-bit source and
destination IDs for up to 256 devices, or large system 16-bit IDs for up to 65,536 devices. For
more information about configurig SRIO, see
“SW1 (Serial Rapid IO Configurations),” on page
38 .
The four SRIO lanes are routed to the AMC fat pipes ports as shown in Table 2-4 .
Table 2-4: SERDES Port Mapping
AMC FatPipes
Port
TXRX{4} TXRX{5} TXRX{6} TXRX{7} TXRX{8} TXRX{9} TXRX{10} TXRX{11}
MPC8641D
PCIe Port
(Build option 1) SD1{0}
(PCIe) SD1{1}
(PCIe) SD1{2}
(PCIe) SD1{3}
(PCIe) SD1{4}
(PCIe) SD1{5}
(PCIe) SD1{6}
(PCIe) SD1{7}
(PCIe)
MPC8641D
SRIO Port
(Build option 3) SD2{0}
(SRIO) SD2{1}
(SRIO) SD2{2}
(SRIO) SD2{3}
(SRIO) --- --- --- ---
MPC8641D
PCIe/SRIO Port
(Build option 4) SD1{0}
(PCIe) SD1{1}
(PCIe) SD1{2}
(PCIe) SD1{3}
(PCIe) SD2{0}
(SRIO) SD2{1}
(SRIO) SD2{2}
(SRIO) SD2{3}
(SRIO)