Chapter 7: Programmable Registers
92
Register 10
This register provides the custom address offset 10d, Ah.
WDOG_INT_EN
Writing:
• 1 to this bit enables the watchdog timer to
•cause an interrupt (IRQ7) to the processor
•set WDOG_FAIL_STS_CLR = 1b
•set the watchdog timer fail latch
• 0 to this bit disables this capability
Reading:
• 1 at this bit indicates that the watchdog timer causes an interrupt when it times
out
• 0 at this bit indicates that watchdog timer does not cause an interrupt when it
times out
WDOG_FAIL_STS_CLR
Writing:
• 1 to this bit clears the internal watchdog interrupt (fail) status latch
• 0 to this bit has no affect
Reading:
• 1 at this bit indicates that the WDOG_INT_EN = 1b, the watchdog timer has
caused an interrupt, and the watchdog timer fail latch is set
• 0 at this bit indicates that the watchdog timer interrupt status is cleared
Table 7-22:
Custom Address Offset 10d, Ah - Bits
7
6
5
4
3
2
1
0
RW (00h) H
WDOG_LDATA
Table 7-23:
Custom Address Offset 10d, Ah - Description
Name
Description
WDOG_LDATA
• The lower 8 bits of the watchdog timer are loaded with this byte when the
watchdog load bit is written with 1. This byte is hexadecimal data and
represents a multiple of 26 mS of time.
• Reading this register returns the value last written to this address, or the
default value if a power reset occurs
Table 7-21:
Custom Address Offset 9d, 9h - Description (Continued)
Name
Description
Содержание AMC131
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