Chapter 7: Programmable Registers
96
Register 18
This register is reserved and reads all zeros.
Register 19
This register provides the custom address offset 19, 13h
Table 7-37:
Custom Address Offset 19, 13h - Bits
7
6
5
4
3
2
1
0
RO (0)
R/W (0)
RO
0x0
IRQ7_ST
0x0
IRQ5_ST
0x0
SEL_CPU
_COMPO
RT
CONSOLE
_REDIRE
CT
Table 7-38:
Custom Address Offset 19, 13h - Description
Name
Description
CONSOLE_REDIRECT
Reading:
• 1 at this bit means that CPU1 has the focus of the front panel console port
• 0 at this bit means that the MMC has the focus of the front panel console port
SEL_CPU_COMPORT
Reading/Writing:
• 0 at this bit means that the serial console port mux selection is controlled by the
MMC.
• 1 at this bit means that the board logic tries to override the MMC and force the
port to be directed to the MPC8641D.
IRQ5_ST
This is the CPU1 IRQ5 line status for the single break detect interrupt.
Reading:
• 1 at this bit means there is a single break detect interrupt active in the PAL.
Output to the CPU may be masked
• 0 at this bit means there is no single break detect interrupt active in the PAL
IRQ7_ST
This is the CPU1 IRQ7 line status for the watchdog interrupt.
Reading:
• 1 at this bit means there is a watchdog interrupt active in the PAL. Output to the
CPU may be masked
• 0 at this bit means there is no watchdog interrupt active in the PAL
Содержание AMC131
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