Chapter 7: Programmable Registers
90
Register 8
This register provides the custom address offset 8d, 8h.
Table 7-18:
Custom Address Offset 8d, 8h - Bits
7
6
5
4
3
2
1
0
RO (0)
RO (0)
RO (0)
RO (0)
RO (0)
RW (0) H
RW (0) H
RW (0) H
0
0
0
0
0
SBREAK_INT_
STS _CLR
SBREAK_INT_
EN
DBREAK_
RST_EN
Table 7-19:
Custom Address Offset 8d, 8h - Description
Name
Description
DBREAK_RST_EN
Writing:
• 1 to this bit enables the double-break detector. Two sequential breaks from
the RS232 interface cause a hard reset pulse to be generated.
• 0 to this bit disables this feature.
SBREAK_INT_EN
Writing:
• 1 to this bit enables the single-break detector. A payload processor interrupt
(IRQ5) is generated to inform the processor that this event has occurred, so
this processor can take the appropriate action. A single break from the
RS232 interface indicates that the console port focus is to change to the next
processor.
• 0 to this bit disables this interrupt.
SBREAK_INT_STS_CLR
Writing:
• 1 to this bit clears the SBREAK status bit.
• 0 to this bit has no affect
Reading:
• 1 at this bit indicates that SBREAK_INT_EN = 1b and a single-break event
(and not a double-break event) is detected
• 0 at this bit indicates that the SBREAK interrupt status bit is cleared
Содержание AMC131
Страница 4: ...4 ...
Страница 10: ...Contents 10 ...
Страница 14: ...Tables 14 ...
Страница 16: ...Figures 16 ...
Страница 32: ...Chapter 2 Introduction 32 ...
Страница 42: ...Chapter 3 Getting Started 42 ...
Страница 82: ...Chapter 6 Reset Configuration 82 ...
Страница 98: ...Chapter 7 Programmable Registers 98 ...