Custom Register Summary
97
Register 20-23
This register provides the custom address offset 20d-23d, 14h-17h.
Notes:
1. These bits are readable and set to 0 by board reset.
2. Not all writes are successful; see LOCKED bit description.
3. All writes to the READY bit are considered valid, unlike the LOCKED bit and COREx_FLAG bits.
Table 7-39:
Custom Address Offset 20d-23d, 14h-17h - Bits
7
6
5
4
3
2
1
0
RW (0) H
RW (0) H
RO (0)
RO (0)
RW (0) H
RW (0) H
RW (0) H
RW (0) H
LOCKED
READY
0
0
CORE3_
FLAG
CORE2_
FLAG
CORE1_
FLAG
CORE0_
FLAG
Table 7-40:
Custom Address Offset 20d-23d, 14h-17h - Description
Name
Description
Notes
CORE0_FLAG
Successfully writing this register causes this bit to change as follows:
CORE0_FLAG = XOR (CORE0_FLAG, DATA[0]
1, 2
CORE1_FLAG
Successfully writing this register causes this bit to change as follows:
CORE1_FLAG = XOR (CORE1_FLAG, DATA[1]
1, 2
CORE2_FLAG
Successfully writing this register causes this bit to change as follows:
CORE2_FLAG = XOR (CORE2_FLAG, DATA[2]
1, 2
CORE3_FLAG
Successfully writing this register causes this bit to change as follows:
CORE3_FLAG = XOR (CORE3_FLAG, DATA[3]
1, 2
READY
Writing:
• 1 to this bit unconditionally toggles the value
• 0 to this bit has no effect
1, 3
LOCKED
LOCKED contributes to forming a write enable for the register (except
READY bit).
Writes are enabled when any of the following is true:
• LOCKED is 0 and DATA[7] being written is 0 (semaphore is unlocked,
resource is multi-access)
• LOCKED is 0 and DATA[3:0] being written is 0000 (semaphore is
unlocked, resource is unused)
• LOCKED is 1 and DATA[3:0] being written is CORE[3:0]_FLAG
(semaphore is locked and will be unlocked following the write)
Содержание AMC131
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