Phytec phyCORE-i.MX 6, Руководство по оборудованию

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General Purpose I/O
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PHYTEC Messtechnik GmbH 2016 L-808e_2
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10 General Purpose I/Os
Table 23 lists all pins not used by any other of the interfaces described explicitly in this
manual and which therefore can be used as GPIO without harming other features of the
phyCORE-i.MX 6.
Pin # Signal ST Voltage Domain Description
X1A25 X_EIM_DA13 I/O VDD_3V3_LOGIC EIM address/data 13; GPIO3_13
X1A42 X_EIM_BCLK O VDD_3V3_LOGIC EIM burst block; GPIO6_31
X1B26 X_EIM_DA14 I/O VDD_3V3_LOGIC EIM address/data 14; GPIO3_14
X1B27 X_EIM_DA15 I/O VDD_3V3_LOGIC EIM address/data 15; GPIO3_15
X1B44 X_EIM_EB1 O VDD_3V3_LOGIC EIM enable byte 1; GPIO2_29
X1C16 X_SPDIF_OUT O VDD_3V3_LOGIC SPDIF output; GPIO7_12
X1C17 X_PWM1_OUT O VDD_3V3_LOGIC PWM1 output; GPIO1_09
X1D13 X_KEY_COL2 I VDD_3V3_LOGIC Keypad column 2; GPIO4_10
Table 23: Location of GPIO Pins
Beside these pins, most of the i.MX 6 signals which are connected directly to the module
connector can be configured to act as GPIO, due to the multiplexing functionality of most
controller pins.
Caution!
Depending on the boot mode, signals at pins X1A25 (EIM_DA13), X1B26 (EIM_DA14),
X1B27 (EIM_DA15) and X1B44 (EIM_EB1) are latched during boot to determine the device
configuration (
section 5 ). Because of that special care must be taken not to override the
device configuration when using these pins as input. To avoid this danger, the eFUSEs can
be used.