Phytec phyCORE-i.MX 6, Руководство по оборудованию

Страница: 56 / 82

phyCORE
®
-i.MX 6 [PCM-058]
42 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
9.10 PCI Express Interface
The 1-lane PCI Express interface of the phyCORE-i.MX 6 provides PCIe Gen. 2.0
functionality which supports 5 Gbit/s operation. Furthermore the interface is fully
backwards compatible to the 2.5 Gbit/s Gen. 1.1 specification. Additional control signals
which might be required (e.g. “present” and “wake”) can be implemented with GPIOs.
Please refer to the schematic of a suitable Phytec carrier board (e.g.
phyBOARD-Mira i.MX 6) for a circuit example.
Table 22 shows the position of the PCIe signals on the phyCORE-Connector X1.
Pin # Signal ST Voltage Domain Description
X1C11 X_PC PCIe_O i.MX 6 internal PCIe clock lane+
X1C12 X_PCIe0_CLK- PCIe_O i.MX 6 internal PCIe clock lane-
X1C13 X_PCIe_RXP PCIe_I i.MX 6 internal PCIe receive lane+
X1C14 X_PCIe_RXN PCIe_I i.MX 6 internal PCIe receive lane-
X1D10 X_PCIe_TXP PCIe_O i.MX 6 internal PCIe transmit lane+
X1D11 X_PCIe_TXN PCIe_O i.MX 6 internal PCIe transmit lane-
Table 22: PCIe Interface Signal Location